Impact of nanomagnets size on switching behaviour of all spin logic devices

Abstract

Under different nanomagnets' size, switching behaviour of all spin logic (ASL) devices constructed with Co and permalloy (Py) nanomagnets are studied by using the coupled spin-transport/magneto-dynamics model. The results indicate that ASL devices' switching delay and energy dissipation can be reduced by decreasing the thickness of nanomagnets. The switching delay and energy dissipation of PyASL are lower than those of CoASL in a smaller thickness of nanomagnet, but they increase much faster than those of CoASL when the nanomagnets (FM) thickness increases. With the dimensional scaling of nanomagnets, the ASL devices' switching delay and energy dissipation decrease rapidly and the influence of thermal noise become weak. Moreover, under the same nanomagnet volume, ASL devices' switching delay, energy dissipation, and energy barrier can be reduced by decreasing aspect ratio. These findings can provide guidelines for optimising the ASL devices' materials and size.

All‐spin logic XOR gate implementation based on input interface

“…where H k is the magneto-crystalline anisotropy field, H d is the demagnetising field, H th is the random thermal noise [12,21]. At the second step, J is set to zero while V DD is set to a positive value.…”

“…where m i are the normalised magnetisation of FM1 and FM2, I Si is the spin current entering FMs, N si is the number of Bohr magnetons in FMs. Spin injection, transport, and dissipation are described by the spin transport model [12,22,23]. In the spin transport model, currents and voltages are 4 × 1 vectors, namely…”

“…where G is a 4 × 4 spin conductance matrix, and its detailed expression can be found in references [11,12]. G can be divided into two basic categories.…”

“…Especially, all-spin logic (ASL) device does not need extra hardware to implementing spin-to-charge conversion repeatedly, because spin is used at every stage of information processing, transfer, and storage [7]. Thus, ASL device has been proposed as a potential beyond-CMOS option for future digital logic application [8] and has attracted wide attention [9][10][11][12][13][14][15].…”

RS flip‐flop implementation based on all spin logic devices

“…Especially, ASL device does not need extra hardware to implementing spin-to-charge conversion repeatedly because spin is used at every stage of information processing, transfer and storage [8]. Thus, ASL device is relatively simpler than other spintronic devices in structure and is thought to be feasible for logic applications, has attracted wide attention [9][10][11][12][13][14][15][16]. The ASL inverter, buffer, majority gate, full adder, latch and D flip-flop have been proposed [17,18].…”