2014
DOI: 10.1109/tnano.2014.2312482
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Impact of Random Interface Traps and Random Dopants in High-<formula formulatype="inline"><tex Notation="TeX">$k$ </tex></formula>/Metal Gate Junctionless FETs

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Cited by 7 publications
(2 citation statements)
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“…In addition, there is a contrast between the trend of V TH variation and DIBL. The V TH variation induced by traps also results in an increment in SS, which can resist the DIBL according to the research [11]. The channel bottom location '7' is used to characterize the trap location sensitivity along the channel length direction.…”
Section: Resultsmentioning
confidence: 99%
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“…In addition, there is a contrast between the trend of V TH variation and DIBL. The V TH variation induced by traps also results in an increment in SS, which can resist the DIBL according to the research [11]. The channel bottom location '7' is used to characterize the trap location sensitivity along the channel length direction.…”
Section: Resultsmentioning
confidence: 99%
“…The gate-all-around field-effect transistor (GAAFET) has become the prime candidate due to its superior electrostatic integrity and ability to satisfy higher performance requirements [4][5][6]. With continuous device scaling, the impact of process fluctuations, including random dopant fluctuation (RDF) [7][8][9], work-function variation (WFV) [9,10], interface trap fluctuation (ITF) [11,12] and oxide thickness variation (OTV) [13], has become more serious and have been widely studied in planar and multi-gate devices. These process variation sources could lead to significant variability in the critical electrical parameters, such as threshold voltage (V TH ), subthreshold slope (SS), on-state current (I ON ), off-state current (I OFF ), etc.…”
Section: Introductionmentioning
confidence: 99%