Investigation of process variation in vertically stacked gate-all-around nanowire transistor and SRAM circuit

Sun, Yabin; Li, Xianglong; Zhuo, Yue; Liu, Yun; Wang, Teng; Li, Xiaojin; Shi, Yanling; Xu, Jun; Liu, Ziyu

doi:10.1088/1361-6641/abe01b

Cited by 8 publications

(1 citation statement)

References 27 publications

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“…There are few sources of process variations such as gate length and fin thickness brought on by work function variation (WFV), random dopant fluctuations (RDF), line edge roughness (LER), gate edge roughness (GER) and fin edge roughness (FER). The impact of process variations WFV and RDF on GAA-SRAM is investigated in [39]. In the manuscript, the variations due to WFV, RDF, LER, GER and FER are analyzed.…”

Section: Process Variation Effectsmentioning

confidence: 99%

Performance investigation of stacked-channel junctionless Tri-Gate FinFET 8T-SRAM cell

Singh,

Chaudhary,

Dewan

et al. 2024

Eng. Res. Express

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Junctionless FinFET devices are a substitute for conventional FinFET devices due to their less short channel effects and easy manufacturing at sub 22-nm technology node. The manuscript presents an 8T-SRAM cell based on tri-gate junctionless FinFET technology. The FinFET device is designed with source/drain of Si material and the channel as a stack of Si − Si0.75Ge0.25 − Si. The proposed SRAM cell structure consists of a CMOS inverter with stacked p-FinFETs, improving its performance in terms of noise margin and leakage power consumption. The manuscript investigates the variation of Static Noise Margin (SNM), leakage power dissipation and delay with supply voltage to analyze the sub-threshold operation of SRAM cell. The results reveal that the cascaded p-FinFETs minimize the leakage current owing to the stack eﬀect, resulting in improved noise margin and lower leakage power. The stacked p-FinFET devices based SRAM cell achieves 1.11x read noise margin, 1.11x hold noise margin, -1.08x write noise margin and 57.1% less leakage power compared to conventional SRAM cell at 1.0 V. However, it exhibits more delay due to increased resistance and capacitance of the cascaded transistors. The process variation analysis is also performed to investigate the SNM distribution using monte-carlo simulation by taking 10,000 samples. The results indicate that the SRAM cell structures provide higher than 6σ yield at range of supply voltages.

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Section: Process Variation Effectsmentioning

confidence: 99%