Impact of Source/drain Implants on Threshold Voltage Matching in Deep Sub-micron CMOS Technologies

Dubois, Jérôme; Knol, J.; Bolt, M.; Tuinhout, H.P.; Schmitz, Jurriaan; Stolk, P. A.

doi:10.1109/essderc.2002.194883

Cited by 15 publications

(10 citation statements)

References 4 publications

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“…The first term is the conventional mismatch due to mismatch in threshold voltage, with the matching coefficient [12]- [14]. This is a technology-related factor that is roughly proportional to the gate-oxide thickness, saturating in UDSM technologies around 2-3 mV m [13]. The second term is the mismatch in gate current as introduced here.…”

Section: Gate-leakage Matching and Its Implicationsmentioning

confidence: 99%

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Analog circuits in ultra-deep-submicron CMOS

Annema

Nauta

Langevelde

et al. 2005

IEEE J. Solid-State Circuits

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357

149

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Section: Gate-leakage Matching and Its Implicationsmentioning

confidence: 99%

“…Using Appendix B, the tunnel conductance can be readily calculated. The normalized gate conductance is then (13) In strong inversion and weak inversion, respectively, this relation can be approximated by the following ones. Note that the dimensions are correct because of implicit multiplication by appropriate scale factors.…”

Section: Appendix Cmentioning

confidence: 99%

Analog circuits in ultra-deep-submicron CMOS

Annema

Nauta

Langevelde

et al. 2005

IEEE J. Solid-State Circuits

Self Cite

357

149

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“…However, the typically way to minimization is spending area [9,10] which in turn increases power consumption at a given speed, because larger capacitances have to be charged [11]. Gate-leakage mismatch is an extra mismatch source [3] with an area-dependency different from that of conventional matching [9,10,12]. Mismatch of gate leakage current is proportional to the gate current level with in 65nm CMOS a proportionality constant…”

Section: The Impact Of Gate-leakage On Matchingmentioning

confidence: 99%

“…This VT A is a technology-related factor that is roughly proportional to the gate-oxide thickness, saturating in UDSM technologies around 2-3mV m [12]. The second term is the gate current mismatch.…”

Section: The Impact Of Gate-leakage On Matchingmentioning

confidence: 99%

Analog/RF circuit design techniques for nanometerscale IC technologies

Nauta

Annema

Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.

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Abstract:CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin-and thick-oxide transistors. Alternatively low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections.

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“…Incorporating the area-dependency of gate-leakage and noting that the V T -spread factor A vt saturates at thin oxides around 2-3mVµm [4] .…”

mentioning

confidence: 99%