Implant electronics for intraocular epiretinal neuro-stimulators

Lehmann, Torsten; Lovell, Nigel H.; Suaning, Gregg J.; Preston, P.; Wong, Yan T.; Dommel, N.; Jung, Louis H.; Moghe, Y.; Das, Kushal

doi:10.1109/iscas.2008.4541427

Cited by 10 publications

(3 citation statements)

References 13 publications

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“…7. This feature is very useful where signal timing across voltage domains is important, for example in neurostimulators where charge balance between sourcing (from ) and sinking (to ) current is required [14]. The area penalty of the inverters and latch is less than 5% since the area is dominated by the DMOS transistors.…”

Section: B Improvement II -Latchingmentioning

confidence: 99%

Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 $\mu$m HV-CMOS Technology

Moghe¹,

Lehmann

Piessens³

2011

IEEE J. Solid-State Circuits

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134

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We present novel circuits for high-voltage digital level shifting with zero static power consumption. The conventional topology is analysed, showing the strong dependence of speed and dynamic power on circuit area. Novel techniques are shown to circumvent this and speed up the operation of the conventional level-shifter architecture by a factor of 5-10 typically and 30-190 in the worst case. In addition, these circuits use 50% less silicon area and exhibit a factor of 20-80 lower dynamic power consumption typically. Design guidelines and equations are given to make the design robust over process corners, ensuring good production yield. The circuits were fabricated in a 0.35 m high-voltage CMOS process and verified. Due to power and IO speed limitation on the test chip, a special ring oscillator and divider structure was used to measure inherent circuit speed.

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Section: B Improvement II -Latchingmentioning

confidence: 99%

Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 $\mu$m HV-CMOS Technology

Moghe¹,

Lehmann

Piessens³

2011

IEEE J. Solid-State Circuits

Self Cite

134

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“…(1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15) The stimulating electrodes of a subretinal implant are positioned under photoreceptors whereas those of an epiretinal implant are positioned above ganglion cells. In the subretinal implants, (8)(9)(10)(11)(12)(13)(14)(15) passive photodiode array, (9) active photodiode sensors with current amplifiers, (8,11,12) or active pixel circuits, (10,13) have been proposed.…”

Section: Introductionmentioning

confidence: 99%

A CMOS 256-pixel Photovoltaics-powered Implantable Chip with Active Pixel Sensors and Iridium-oxide Electrodes for Subretinal Prostheses

Wu¹,

Kuo²,

Lin³

et al. 2018

Sensors and Materials

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Keywords: divisional power supply scheme, active pixel sensor, photovoltaic cell, CMOS image sensor, biocompatible package A CMOS implantable chip with 256 active pixel sensors (APSs), on-chip photovoltaic cells, and iridium-oxide (IrOx) electrodes is proposed and designed for subretinal prostheses. In the proposed chip, the on-chip electrode surface is deposited with IrOx by RF sputtering and photolithography patterning. The divisional power supply scheme (DPSS) is adopted to generate sufficient stimulation current whereas the APS is used to enhance the image sensitivity. The proposed chip consists of a 16 × 16 photodiode array with 8 DPSS divisions, control signal generator circuits, and photovoltaic cells. It is designed and fabricated into 180 nm CMOS image sensor (CIS) technology and postprocessed with an IrOx coating. From the electrical measurement results, the fabricated chip has a peak output stimulation current of 16.7 μA under the equivalent electrode impedance load. The stimulation frequency is 30.2 Hz and the amount of injected charges at each pixel is 3.5 nC. Both image light sensitivity and injection charges are significantly improved. The surface morphology, crystallinity, charge storage capacity, and biocompatibility of sputtering iridium oxide film (SIROF) were investigated. As a result, the SIROF has desirable physical and electrochemical properties that make it suitable for the neurostimulation electrodes on the 256-pixel implantable chip. The 7-month biocompatibility and charge delivery capability of the fabricated chip have been confirmed by electroretinography (ERG) measurement on a Lanyu minipig in in vivo animal tests.

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“…Related studies include low power CMOS chip designs to drive the electrode matrix, FPGA-based stimulation systems, dense and flexible microelectrode matrix development, low current stimulation technologies, wireless power and data transfer technologies, and micro magnetic stimulation technologies [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19].…”

Section: Introductionmentioning

confidence: 99%

Spatio-Temporal Electrode Mapping and Local Interleaved Stimulation Method (STEMLIS) for Artificial Sight Systems

Özden

Karagöz²

2015

J Bioengineer & Biomedical Sci

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Image processing algorithms play a key role in the development of visual prosthesis systems. In this study, a new electrode stimulation method for retinal implant systems, "Spatio-Temporal Electrode Mapping and Local Interleaved Stimulation (STEMLIS)," is proposed. In this method, the most meaningful spikes that preserve the spatial discrimination in a temporal frame are selected as stimulation data, and phase shifts are applied to all sub electrode groups to minimize undesired electrode interactions. By using this method, both spatial and temporal resolution of stimulation data can be enhanced, since spatio-temporal mapping is used while selecting the stimulation data from a large number of spike data for stimulation of the low-numbered electrode matrix placed on retina surface. The phase delays between the neighboring electrodes are used to introduce interleaved pulses, which minimize the electrical interactions. To evaluate the contribution of the STEMLIS method to perceived image quality, computer based quantitative simulation studies and visual evaluation tests with normal seeing people were performed. For quantitative evaluation, the outputs for the classical method and the STEMLIS method were compared based on the mean squared error (MSE), the histogram similarity ratio (HSR), and edge discrimination parameters. In visual tests, performance of the method was evaluated in terms of contrast discrimination, pattern recognition, text reading and object counting tasks. The subjects reached higher test scores with proposed method and better scores obtained in quantitative comparison. It is concluded that spatio-temporal enhancement of stimulation data can help to improve perceived image quality on visual prostheses.

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Implant electronics for intraocular epiretinal neuro-stimulators

Cited by 10 publications

References 13 publications

Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 $\mu$m HV-CMOS Technology

Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 $\mu$m HV-CMOS Technology

A CMOS 256-pixel Photovoltaics-powered Implantable Chip with Active Pixel Sensors and Iridium-oxide Electrodes for Subretinal Prostheses

Spatio-Temporal Electrode Mapping and Local Interleaved Stimulation Method (STEMLIS) for Artificial Sight Systems

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