Implantation-free edge termination structures in vertical GaN power diodes

Abstract

Gallium nitride (GaN) is a promising candidate for power applications, due to its superior electrical properties such as high critical breakdown field and saturation drift velocity. The recent emergence of GaN substrates with low defect densities has made it feasible to develop efficient vertical GaN power diodes. However, the breakdown voltage of these diodes is far from the theoretical value, due to the lack of suitable edge termination techniques in GaN such as junction termination extension (JTE). This is attributed to the processing challenges in fabricating GaN power diodes where it is difficult to form p-type regions through implantation. This work addresses this challenge and proposes the design, optimization, and a comprehensive design methodology for implantation-free, edge termination techniques such as field plate (FP), single and multi-etch JTE, and a hybrid FP-JTE structure, suitable for vertical GaN diodes. The proposed approaches demonstrate that close to theoretical breakdown voltages (>80%) are achievable, with greater area efficiency, simple processing, and high tolerance in process variation.

An Optimized Vertical GaN Parallel Split Gate Trench MOSFET Device Structure for Improved Switching Performance

“…The device characteristics were calibrated amongst the experimental results of a fabricated TG-MOSFET, described by R. Li et al [23] using TCAD simulation [41]. The TCAD device simulation methodology and important physics models have been reported in the previous work [27], [35]- [38], as shown in Table 1. TCAD Sentaurus provides users with access to a wide variety of physical models, each of which is designed to explain the physical behavior of semiconductor devices as precisely as is technically feasible in relation to the fabricated device.…”

Design of selective-area growth compatible fully-vertical GaN p-i-n diodes with dielectric vertical sidewall appended edge termination schemes

“…While a plethora of ET schemes [2][3][4][5][6][7][8][9][10][11][12][13][14] have been proposed for GaN power devices, they are riddled with various issues. For example, single-zone junction termination extension (SZ-JTE) schemes for GaN platform [3] appear attractive at first glance.…”

“…For example, if we consider the triple-zone JTE (TZ-JTE) structure in figure 2(c), we not only need to control L JTE,i (i = 1, 2, 3), we also need to maintain precisely each of the ratios N P /N JTE,1 , N JTE,1 /N JTE,2 , and N JTE,2 /N JTE,3 , which is quite difficult in practice, because of close proximity of N JTE,i values [6]. Another option is the ET schemes based on etched p-base [7]. These schemes can reliably provide reverse blocking efficiency, η br (= V br /V br,id ) only up to 80%.…”

“…For reliable performance in reverse blocking mode, a power device, such as, a GaN p-i-n diode should have a few desired attributes like simplicity in device processing, large V br , and low leakage current. Various edge termination (ET) techniques for GaN power devices have been proposed and/or experimentally demonstrated [2][3][4][5][6][7][8][9][10][11][12][13][14]. However, these reported ET schemes suffer from a wide range of issues including designed and experimentally reported V br values much lower than ideal parallel-plane breakdown voltage, V br,id (or projected V br values), complicated or stringent device processing requirements, dependence on processing methodologies prone to lattice damage and leakage, vulnerability to surface charges [6,7,14], and narrow ET doping window to achieve optimum V br .…”

“…Various edge termination (ET) techniques for GaN power devices have been proposed and/or experimentally demonstrated [2][3][4][5][6][7][8][9][10][11][12][13][14]. However, these reported ET schemes suffer from a wide range of issues including designed and experimentally reported V br values much lower than ideal parallel-plane breakdown voltage, V br,id (or projected V br values), complicated or stringent device processing requirements, dependence on processing methodologies prone to lattice damage and leakage, vulnerability to surface charges [6,7,14], and narrow ET doping window to achieve optimum V br . Therefore, simple, robust, low-leakage, and reliable ET schemes capable of achieving V br,id are essential to establishing GaN at the forefront of the booming power electronics industry.…”