No abstract

In this work, we develop highly efficient ET schemes based on a selective-area processing methodology that can effectively stymie device leakage, resulting in reliable device operation. In particular, we demonstrate plasma-assisted molecular-beam epitaxy (PAMBE) facilitated silicon nitride shadowed selective-area growth (SNS-SAG) technique, capable of producing smooth GaN interfaces and sidewalls as an enabling technology for high-performance vertical GaN power devices. SNS-SAG is shown to reduce leakage current by at least four orders of magnitude compared to a dry etched device. Floating guard ring (FGR) and junction termination extension (JTE) based ET designs for GaN p-in diodes for punchthrough operation have been simulated and analyzed in order to develop SNS-SAG compatible space-modulated junction termination extension (SM-JTE) schemes capable of achieving maximum reverse blocking efficiency > 98% while maintaining a wide doping window of up to ∼ 5×10 17 cm −3 at a minimum reverse blocking efficiency of ∼ 90% extending well into high 10 17 cm −3 range (∼ 8×10 17 cm −3). In conjunction with the proposed SNS-SAG technique, SM-JTE schemes have the prospects to offer reliable GaN vertical power device operation.

No abstract

High melt temperature and thermal decomposition prevent the use of standard bulk semiconductor crystal growth processes for the production of GaN. We have employed a hydrostatic pressure system to grow GaN crystals. An ultrahigh pressure, high temperature process was developed using a solid-phase nitrogen source to form GaN crystals in a Ga metal melt. Using a thermal gradient diffusion process, in which nitrogen dissolves in the high temperature region of the metal melt and diffuses to the lower temperature, lower solubility region, high quality crystals up to ϳ1 mm in size were formed, as determined by scanning electron microscopy, x-ray diffraction, and micro-Raman analysis.

While a slew of edge termination schemes for gallium nitride (GaN) power devices have been proposed and experimentally demonstrated to date, all of them suffer from the inability to achieve breakdown voltage close to ideal parallel-plane breakdown voltage. Further, they are exclusively processed using implantation or dry etching based methods, both of which are known to introduce additional defects and lattice damage leading to large leakage components. In this work, we develop and design novel dielectric vertical sidewall appended edge termination (DiVSET) schemes that are surface-charge resilient and capable of achieving ideal parallel-plane breakdown voltage. These edge termination schemes are compatible with plasma-assisted molecular-beam epitaxy facilitated silicon nitride shadowed selective-area growth (SNS-SAG) processing protocol, recently developed by us. The SNS-SAG protocol is uniquely capable of processing smooth, lattice damage-free GaN interfaces and vertical sidewalls that can reduce the leakage current by several orders of magnitude compared to conventional implant and dry etching based GaN processing. Together with the SNS-SAG processing, the DiVSET schemes offer an enabling technology for high-performance ultra-low leakage GaN power devices.