Implementation of a real-time algorithm for maternal and fetal heart rate monitoring in a digital signal controller platform

Abstract

An LMS-based algorithm to monitor fetal and maternal heart rate in real time was implemented and evaluated on a development platform. Hardware has three modules: dsPIC30F digital signal controller, a low-noise analog front end and a storage stage. They were evaluated using on-chip debugging tools and a patient simulator. Algorithm performance was tested using simulation tools and real data. Other measures like process run-times and power consumption, were analyzed to evaluate the design feasibility. Dataset was conformed by 25 annotated records from different gestational age pregnant women. Sensitivity and accuracy were used as performance measures. In general, sensitivity was high for maternal (95.3%) and fetal (87.1%) detections. Results showed that the chosen architecture can run efficiently the algorithm processes, obtaining high detection rates under appropriate SNR conditions.

Efficient implementation of LMS adaptive filter‐based FECG extraction on an FPGA

“…aThe system proposed by Ortega et al [12] consumes 1 W, for the current absorption of 200 mA and supply of 5 V, at 30 MHz operating frequency.…”

“…LabVIEW FPGA module was used to generate the hardware design. Arias‐Ortega et al [12] implemented the LMS‐AF on a digital signal controller, used a low‐noise analogue front end to achieve 93.1% accuracy and 87.1% sensitivity. In [13], the authors implemented an LMS‐AF‐based FECG extraction system on an FPGA.…”