Implementation of AES on FPGA

Abstract

Advanced Encryption Standard (AES) a National Institute of Standards and Technology specification is an approved cryptographic algorithm that can be used for securing electronic data. Reprogrammable devices such as Field Programmable Gate Arrays (FPGA) are highly attractive option for hardware implementations of cryptographic algorithm AES as they offer a quicker and more customizable solution. This paper proposes an efficient FPGA implementation of advanced encryption standard (AES). We implement the AES encryption algorithm on Xilinx Spartan-3 FPGA and decryption is done on PC. The coding for encryption is done in VHDL language and for decryption in Visual Basic. To implement AES Rijndael algorithm on FPGA plain text of 128 bit data is considered. Advanced Encryption Standard (AES) RIJNDAEL on FPGA offers a better performance than any other cryptographic algorithms.

High Speed Area Efficient FPGA Implementation of AES Algorithm

“…Yewale Minal J. et al [13] proposed implementation of AES encryption using VHDL and decryption using Visual basic. With this approach, 1403 slices are utilized at maximum operating frequency of 160.875 MHz and it has a throughput of 2.059 Gbps.…”