Implementation of array structured maximum likelihood decoders

In this paper, we present a rad1x-2~ Viterbi decoding with Transpose Path Metric (TPM) processor. The TPM processor can provide a permutation function for state rearrangement with simple local interconnection.For interconnection realization, the routing complexity is less than that of the delay-commutator reported previously. In addition, a higher memory length Viterbi processor can be constructed with lower radix-2k modules. With features of modulation and cell regularity, the r a d i ~-2 ~ Viterbi decoding with TPM processor is very suitable for VLST implementation,

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The radix-2/sup k/ Viterbi decoding with transpose path metric processor

Lee

Chen²,

Chen

Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems

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A VLSI architecture for radix-2/sup k/ Viterbi decoding with transpose algorithm

Lee¹,

Chen²,

Chen³

1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers

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The paper presents a novel transpose path metric (TPM) algoritluii to rcduce tlie interconnection routing complexity for ~1 d i x -2 ~ Viterbi decoder. With simple local interconnections, the algorithm can provide a permutation function for state rcarrangenient in a transpose strategy. With features of modulation and regularity, this algorithm is v e n suitable for VLSI implementation; consequently, a larger memory Icngth VA decoder can be constructed with several siiiallcr mciiiory length modules Finally, a VLSI architecture for 16-states radix-4 VA decoder using TPM lias been developed.

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Implementation of array structured maximum likelihood decoders

Cited by 2 publications

References 16 publications

The radix-2/sup k/ Viterbi decoding with transpose path metric processor

The radix-2/sup k/ Viterbi decoding with transpose path metric processor

A VLSI architecture for radix-2/sup k/ Viterbi decoding with transpose algorithm

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