Implementation of Chaotic System using FPGA

Al-Musawi, Wisal Adnan; Wali, Wasan A.; Al-Ibadi, Mohammed A.

doi:10.1109/acirs52449.2021.9519360

Cited by 4 publications

(1 citation statement)

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“…Nevertheless, FPGAs (Field Programmable Gate Arrays) possess the potential to function in a parallel manner in relation to hardware, setting them apart from conventional CPUs. Operations in FPGAs are partitioned into segments, allowing for concurrent execution of many operations [12,13]. Fig.…”

Section: Introductionmentioning

confidence: 99%

Real Time FPGA Implementation of a High Speed for Video Encryption and Decryption System with High Level Synthesis Tools

Alhomoud

2024

IJACSA

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The development of communication networks has made information security more important than ever for both transmission and storage. Since the majority of networks involve images, image security is becoming a difficult challenge. In order to provide real-time image encryption and decryption, this study suggests an FPGA implementation of a video cryptosystem that has been well-optimized based on high level synthesis. The MATLAB HDL coder and Vivado Tools from Xilinx are used in the design, implementation, and validation of the algorithm on the Xilinx Zynq FPGA platform. Low resource consumption and pipeline processing are well-suited to the hardware architecture. For real-time applications involving secret picture encryption and decryption, the suggested hardware approach is widely utilized. This study suggests an implementation of the encryption-decryption system that is both very efficient and areaoptimized. A unique high-level synthesis (HLS) design technique based on application-specific bit widths for intermediate data nodes was used to realize the proposed implementation. For HLS, MATLAB HDL coder was used to generate register transfer level RTL design. Using Vivado software, the RTL design was implemented on the Xilinx ZedBoard, and its functioning was tested in real time using an input video stream. The results produced are faster and more area-efficient (target FPGA has fewer gates than before) than those of earlier solutions for the same target board.

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Section: Introductionmentioning

confidence: 99%