Implementation of High Power RF Devices with Hybrid Workfunction and OxideThickness in 22nm Low-Power FinFET Technology

Lee, H.-J.; Sell, B.; Zhang, Y.; Morarka, Saurabh; Rami, Said; Yu, Qiang; Weiß, M.; Liu, G.; Armstrong, M.; Su, Chun-Yi; Ali, D.

doi:10.1109/iedm19573.2019.8993647

Cited by 11 publications

(8 citation statements)

References 3 publications

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“…Conversely, with a long L ch and a short L ext , the lateral electric field distribution may not be sufficient. Therefore, while fixing the total carrier transport length at L ch of HyPowerFF (160 nm) [16], both L ch and L ext of the C-DeFF are set to be 80 nm, respectively. Thus, with the lowest R on , the C-DeFF achieves the targeted V BD of 7.3 V at L ch = L ext = 80 nm.…”

Section: Simulation Methods and Device Designmentioning

confidence: 99%

“…In order to overcome this trade-off, DE structures with high-k field plate (FP) [13], fin/planar hybrid [14], and shallow trench isolation laterally diffused MOSFET (STI LDMOS) [15] have been suggested. Without DE structure, Hybrid workfunction and oxide thickness Low-Power FinFET (HyPowerFF) has also been reported [16]. In short, HyPowrFF and Hybrid FinFET have a relatively high conductivity but low V BD , STI LDMOS has a comparatively high V BD but a low conductivity.…”

Section: Introductionmentioning

confidence: 99%

“…The structure, namely dual material gate (DMG) and high-k field plate-DeFinFET (DF-DeFF), utilizes a DMG and a high-k FP, and they are effectively combined into the DeFinFET. In the following, the device performance will be verified by comparing the figures of merit in DC and RF performances of DF-DeFF with the Conventional-DeFinFET (C-DeFF) and the recently proposed devices, such as Hybrid FinFET [14], STI LDMOS [15], and HyPowerFF [16].…”

Section: Introductionmentioning

confidence: 99%

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A drain extended FinFET with enhanced DC/RF performance for high-voltage RF applications

Kim

Park

et al. 2022

Semicond. Sci. Technol.

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A drain-extended (DE) FinFET with a dual material gate (DMG) and a high-k field plate (FP), named DF-DeFF, is proposed for high-voltage RF applications. The FP induces the charge variation in the drain extension, which appears as either the extended depletion in the gate-off state or the electron accumulation in the gate-on state. Along with the FP, the DMG forms a step-like potential variation along the channel, which leads to electron acceleration and the screening effect on the drain-to-source voltage (VDS). These effects give significant advantages to the DC characteristics, including breakdown voltage (VBD) and on-resistance (Ron), and the RF characteristics, including transconductance (gm) and output-resistance (ro). Compared to the latest high-voltage RF FinFETs, the DF-DeFF shows a drastic improvement in the major performance indicators such as VBD, cut-off frequency (fT), and maximum oscillation frequency (fMAX). These results indicate that DF-DeFF is a FinFET with sufficient competitiveness even in high voltage circumstances.

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Section: Simulation Methods and Device Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A drain extended FinFET with enhanced DC/RF performance for high-voltage RF applications

Kim

Park

et al. 2022

Semicond. Sci. Technol.

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“…But it is challenging to scale down the devices while maintaining analog/RF performances in order to contain all chipsets including longterm evolution and 5G bands within a small mobile device. Meanwhile, planar MOSFETs adopting dual workfunction (WF) scheme, so called cascode MOSFETs, have been proposed to increase transconductance (G m ) and output resistance (R o ), eventually attaining high intrinsic gain (A V = G m R o ) [6]- [8]. In addition, dual-WF FinFETs have been implemented and showed larger A V , cutoff frequency (F t ), and maximum frequency (F max ) than conventional (conv-) FinFETs [8].…”

Section: Introductionmentioning

confidence: 99%

“…Meanwhile, planar MOSFETs adopting dual workfunction (WF) scheme, so called cascode MOSFETs, have been proposed to increase transconductance (G m ) and output resistance (R o ), eventually attaining high intrinsic gain (A V = G m R o ) [6]- [8]. In addition, dual-WF FinFETs have been implemented and showed larger A V , cutoff frequency (F t ), and maximum frequency (F max ) than conventional (conv-) FinFETs [8]. However, this dual-WF scheme requires sufficiently long channel length to utilize the discontinuous lateral energy band by pinning source-side potential for high injection velocity.…”

Section: Introductionmentioning

confidence: 99%

A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications

Yoon

Baek

2020

IEEE Access

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A novel sub-5-nm node folded cascode structure using dual workfunction (WF) scheme was proposed using fully-calibrated TCAD. Feasible process flows of the cascode device were adopted from those of nanosheet FETs (NSFETs) and complementary FETs. Key process flows were depositing two different separate spacers and etching one spacer selectively, depositing oxide layer in between source/drain epitaxial growths for electrical isolation, and fill-CMP-etch back sequence for dual-WF. The folded cascode device consists of two or three FETs in series, designated as 2-CAS or 3-CAS respectively, under the same active area. Conventional three-stacked NSFETs have larger transconductance (G m) than 2-CAS and 3-CAS, but the cascode devices have much larger output resistance (R o) by dual-WF scheme and thus achieve larger intrinsic gain (A V = G m R o). Smaller G m and larger gate capacitance for the cascode devices decrease the cutoff frequency. But smaller gate-to-drain capacitance by shrunk drain epi along with large R o increases the maximum frequency (F max). Especially, 2-CAS has larger A V and F max than conventional NSFETs for all the NS widths of 20, 30, and 40 nm and at all the operation voltages of 0.6, 0.7, and 0.8 V, promising for low power mobile applications.

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Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques

Jaisawal

Rathore

Kondekar

et al. 2022

Semicond. Sci. Technol.

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One of the severe issues of the downscaling of semiconductor devices is the threshold voltage reduction which significantly increases the leakage current. Thus, high threshold voltage (HVT) techniques are required to bring down the leakage hike for improved performances. In this paper, for the first time, we investigate the analog/RF and linearity performances of silicon (Si) FinFET by employing HVT techniques. Using well-calibrated TCAD models, to mitigate the leakage current, we analyzed the following approach to get HVT: 1) increasing channel doping (Nch′); 2) making drain-side underlap (Ldsu); 3) increasing gate length (Lg′). Two flavors of FinFETs viz Bulk and SOI (silicon-on-insulator) are suitably compared over their baseline counterpart, i.e., without HVTs. A thorough investigation of analog/RF metrics such as transconductance, output resistance, gate capacitance, cut-off frequency, gain-bandwidth, and transconductance-frequency product proves the eminence of Bulk-FinFET over its peer SOI-FinFET. In contrast, SOI-FinFET shows merits in intrinsic gain and linearity such as gm2, gm3, VIP2, VIP3, IIP3, IMD3, and 1-dB compression point. Thus, HVT techniques are worth analyzing for a FinFET architecture employed in analog/RF applications.

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Implementation of High Power RF Devices with Hybrid Workfunction and OxideThickness in 22nm Low-Power FinFET Technology

Cited by 11 publications

References 3 publications

A drain extended FinFET with enhanced DC/RF performance for high-voltage RF applications

A drain extended FinFET with enhanced DC/RF performance for high-voltage RF applications

A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications

Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques

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