Implementation of input data buffering and scheduling methodology for 8 parallel MDC FFT

Locharla, Govinda Rao; Kumar, K Sudeendra; Mahapatra, Kamalakanta; Ari, Samit

doi:10.1109/isvdat.2015.7208107

Cited by 5 publications

(5 citation statements)

References 8 publications

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“…It is clear from the earlier comparison that our design has a good compromise between area, speed, and power. However, to provide more clarity about our design and to eliminate any confusion, we have compared the presented work with the most recent designs for ASIC application such as the work presented in . First, we would like to emphasize that the number of memory instances in our design is large due to the separation of the input and output buffers at every stage.…”

Section: Resultsmentioning

confidence: 99%

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A multi‐mode IFFT/FFT processor for IEEE 802.11ac: design and implementation

Ali

Hamouda

2015

Wireless Communications

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In this paper, we present 64/128/256/512-point inverse fast Fourier transform (IFFT)/FFT processor for single-user and multi-user multiple-input multiple-output orthogonal frequency-division multiplexing based IEEE 802.11ac wireless local area network transceiver. The multi-mode processor is developed by an eight-parallel mixed-radix architecture to efficiently produce full reconfigurability for all multi-user combinations. The proposed design not only supports the operation of IFFT/FFT for 1-8 different data streams operated by different users in case of downlink transmission, but also, it provides different throughput rates to meet IEEE 802.11ac requirements at the minimum possible clock frequency. Moreover, less power is needed in our design compared with traditional software approach. The design is carefully optimized to operate by the minimum wordlengths that fulfill the performance and complexity specifications. The processor is designed and implemented on Xilinx Vertix-5 field programmable gate array technology. Although the maximum clock frequency is 377.84 MHz, the processor is clocked by the operating sampling rate to further reduce the power consumption. At the operation clock rate of 160 MHz, our proposed processor can calculate 512-point FFT with up to eight independent data sequences within 3.2~s meeting IEEE 802.11ac standard requirements.

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Section: Resultsmentioning

confidence: 99%

“…Furthermore, one recent design for the FFT engine of IEEE802.11ac has been presented in . Although this design is an application specific integrated circuit (ASIC) design, it is beneficial to discuss the architecture and to study its convenience to the FPGA environment.…”

Section: Processor Architecturementioning

confidence: 99%

A multi‐mode IFFT/FFT processor for IEEE 802.11ac: design and implementation

Ali

Hamouda

2015

Wireless Communications

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“…According to the IEEE 754 standard [10], the single precision is chosen to represent the floating-point data. The IEEE standard specifies a way in which the three values described can be represented in a 32-bit or a 64-bit binary number, referred to single and double precision, respectively [11,12]. In this project, single precision is selected to function.…”

Section: Floating Point Fft Algorithmmentioning

confidence: 99%

High Resolution Single-Chip Radix II FFT Processor for High- Tech Application

Teymourzadeh¹

2017

Fourier Transforms - High-Tech Application and Current Trends

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Electrical motors are vital components of many industrial processes and their operation failure leads losing in production line. Motor functionality and its behavior should be monitored to avoid production failure catastrophe. Hence, a high-tech DSP processor is a significant method for electrical harmonic analysis that can be realized as embedded systems. This chapter introduces principal embedded design of novel high-tech 1024-point FFT processor architecture for high performance harmonic measurement techniques. In FFT processor algorithm pipelining and parallel implementation are incorporated in order to enhance the performance. The proposed FFT makes use of floating point to realize higher precision FFT. Since floating-point architecture limits the maximum clock frequency and increases the power consumption, the chapter focuses on improving the speed, area, resolution and power consumption, as well as latency for the FFT. It illustrates very large-scale integration (VLSI) implementation of the floating-point parallel pipelined (FPP) 1024-point Radix II FFT processor with applying novel architecture that makes use of only single butterfly incorporation of intelligent controller. The functionality of the conventional Radix II FFT was verified as embedded in FPGA prototyping. For area and power consumption, the proposed Radix II FPP-FFT was optimized in ASIC under Silterra 0.18 µm and Mimos 0.35 µm technology libraries.

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“…16 and WPAN/WLAN/WMAN. In our earlier work [18,19], the pretransform and post-transform data scheduling, reordering methodologies for FFT/IFFT are presented to meet IEEE 802.11ac requirements.…”

Section: Introductionmentioning

confidence: 99%

“…Most of the FFT/IFFT designs reported so far in the literature are intended for the various applications like IEEE 802.11n/a/ad, IEEE 802.15, IEEE 802.16 and WPAN/WLAN/WMAN. In our earlier work [18, 19], the pre‐transform and post‐transform data scheduling, reordering methodologies for FFT/IFFT are presented to meet IEEE 802.11ac requirements.…”

Section: Introductionmentioning

confidence: 99%

Variable length mixed radix MDC FFT/IFFT processor for MIMO‐OFDM application

Locharla

Mahapatra

Ari

2017

IET Computers & Digital Techniques

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This study presents a variable length multi-path delay commutator fast Fourier transform (FFT)/inverse FFT (IFFT) architecture for a multiple input multiple output orthogonal frequency division multiplexing system. It supports the FFT/ IFFT lengths of 512/256/128/64 samples to process each symbol carried by eight spatial streams and achieves a speed of 160 MHz to meet the IEEE 802.11ac timing requirements. A resource scheduling methodology to minimise the hardware complexity of the design is proposed and adopted in the architecture presented. A novel stagger word length strategy is also proposed and applied to achieve the better accuracy with lesser hardware. Here, the signal to quantisation noise ratio of 57.23 dB is obtained. The twiddle coefficient storage space is significantly compressed to achieve the coefficient generation with reduced hardware. The design is implemented using the TSMC-65 nm complementary metal oxide semiconductor technology with a supply voltage of 1 V at 160 MHz. The implementation results show that the architecture has a gate count of 3,48,013 with power consumption of 105.1 mW and area of 0.492 mm 2. The hardware complexity and performance of the design are compared with earlier reported architectures. It is observed that the proposed design achieves better performance in terms of hardware complexity and normalised energy for the given specifications.

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Implementation of input data buffering and scheduling methodology for 8 parallel MDC FFT

Cited by 5 publications

References 8 publications

A multi‐mode IFFT/FFT processor for IEEE 802.11ac: design and implementation

A multi‐mode IFFT/FFT processor for IEEE 802.11ac: design and implementation

High Resolution Single-Chip Radix II FFT Processor for High- Tech Application

Variable length mixed radix MDC FFT/IFFT processor for MIMO‐OFDM application

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