Implementation of multiple PID controllers on FPGA

Aboelaze, Mokhtar; Shehata, Mohamed

doi:10.1109/icecs.2015.7440344

Cited by 7 publications

(3 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…An embedded architecture was used to implement PID controller for DC torquers with embedded DSP TMS320LF240 in 12 for mobile robots. FPGA was used in 13, 16,17,21 where PID controllers were implemented for different applications. An AVR microcontroller was used to implement controller for brushless DC motor in 14 , where a double closed loop namely speed and current control loops were realised.…”

Section: Related Workmentioning

confidence: 99%

Efficient Embedded Hardware Architecture for Stabilised Tracking Sighting System of Armoured Fighting Vehicles

Verma¹,

Ghosh²,

Marathe³

et al. 2019

Def. Sc. Jl.

View full text Add to dashboard Cite

A line-of-sight stabilised sighting system, capable of target tracking and video stabilisation is a prime requirement of any armoured fighting tank vehicle for military surveillance and weapon firing. Typically, such sighting systems have three prime electro-optical sensors i.e. day camera for viewing in day conditions, thermal camera for night viewing and eye-safe laser range finder for obtaining the target range. For laser guided missile firing, additional laser target designator may be a part of sighting system. This sighting system provides necessary parameters for the fire control computer to compute ballistic offsets to fire conventional ammunition or fire missile. System demands simultaneous interactions with electro-optical sensors, servo sensors, actuators, multi-function display for man-machine interface, fire control computer, logic controller and other sub-systems of tank. Therefore, a complex embedded electronics hardware is needed to respond in real time for such system. An efficient electronics embedded hardware architecture is presented here for the development of this type of sighting system. This hardware has been developed around SHARC 21369 processor and FPGA. A performance evaluation scheme is also presented for this sighting system based on the developed hardware.

show abstract

Section: Related Workmentioning

confidence: 99%

Efficient Embedded Hardware Architecture for Stabilised Tracking Sighting System of Armoured Fighting Vehicles

Verma¹,

Ghosh²,

Marathe³

et al. 2019

Def. Sc. Jl.

View full text Add to dashboard Cite

show abstract

“…Researchers are eager to find an optimized solution for PLCs in terms of FPGAs [15]. Researchers have also started to realize PID controllers using FPGAs, as discussed in [16]. This work proposed a method in which more than one closed-loop control system will be concurrently processed by the dedicated hardware resources of the FPGA without compromising the scan time of the PLC.…”

Section: Introductionmentioning

confidence: 99%

Scan Time Reduction of PLCs by Dedicated Parallel-Execution Multiple PID Controllers Using an FPGA

Dhanabalan¹,

Selvi²,

Mahdal

2022

Sensors

View full text Add to dashboard Cite

A programmable logic controller (PLC) executes a ladder diagram (LD) using input and output modules. An LD also has PID controller function blocks. It contains as many PID function blocks as the number of process parameters to be controlled. Adding more process parameters slows down PLC scan time. Process parameters are measured as analog signals. The analog input module in the PLC converts these analog signals into digital signals and forwards them to the PID controller as inputs. In this research work, a field-programmable gate array (FPGA)-based multiple PID controller is proposed to retain PLC scan time at a lower value. Concurrent execution of multiple PID controllers was assured by assigning separate FPGA hardware resources for every PID controller. Digital input to the PID controller is routed by the novel idea of analog to digital conversion (ADC), performed using a digital to analog converter (DAC), comparator, and FPGA. ADC combined with dedicated PID controller logic in an FPGA for every closed-loop control system confirms concurrent execution of multiple PID controllers. The time required to execute two closed-loop controls was identified as 18.96000004 ms. This design can be used either with or without a PLC.

show abstract

“…An essential characteristic of such systems is unpredictability of their critical states. Then this object can't defined by clean mathematical definitions for example by differential equations [1][2][3][4].…”

Section: Introductionmentioning

confidence: 99%

A real time control system for balancing a ball on a platform with FPGA parallel implementation

Samotyy

Telenyk

Kravets

et al. 2018

View full text Add to dashboard Cite

In this paper, a new PID-regulator based solution to the scientific and practical problem of increasing the accuracy of regulating the position of a ball on a platform in real time is proposed. A transfer function for balancing a ball on a platform is developed. A PID-regulator for balancing a ball on a platform is synthesized. A PID-regulator implementation on FPGA with parallel calculations is designed. An increased accuracy of regulating the position of a ball on a platform is approved by natural simulation.

show abstract

Implementation of multiple PID controllers on FPGA

Cited by 7 publications

References 9 publications

Efficient Embedded Hardware Architecture for Stabilised Tracking Sighting System of Armoured Fighting Vehicles

Efficient Embedded Hardware Architecture for Stabilised Tracking Sighting System of Armoured Fighting Vehicles

Scan Time Reduction of PLCs by Dedicated Parallel-Execution Multiple PID Controllers Using an FPGA

A real time control system for balancing a ball on a platform with FPGA parallel implementation

Contact Info

Product

Resources

About