2011
DOI: 10.1007/s10470-011-9765-8
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Implementation of sphere decoder for MIMO-OFDM on FPGAs using high-level synthesis tools

Abstract: In this study we explain the implementation of a sphere detector for spatial multiplexing in broadband wireless systems using high-level synthesis (HLS) tools. These modern FPGA design tools accept C/C?? descriptions as input specifications, and automatically generate a register transfer level (RTL) description for FPGA implementation using traditional FPGA implementation tools. We have used AutoESL's AutoPilot HLS tool to implement this demanding algorithm on a Virtex-5 running at a clock frequency of 225 MHz… Show more

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Cited by 8 publications
(3 citation statements)
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“…The HLS tools are gaining popularity and they are challenging the traditional design approach. There are several studies showing that these tools increase the design productivity and reduce the development time, while producing compet-itive quality of results compared to hand written RTL [29,30].…”
Section: Development Environmentmentioning
confidence: 99%
“…The HLS tools are gaining popularity and they are challenging the traditional design approach. There are several studies showing that these tools increase the design productivity and reduce the development time, while producing compet-itive quality of results compared to hand written RTL [29,30].…”
Section: Development Environmentmentioning
confidence: 99%
“…AutoESL is used to implement applications including compressive sensing [6], stereo matching [7], a sphere detector for broadband wireless systems [8], and real-time HDTV [9]. Catapult-C has been used to implement 64-QAM decoder [10], and a sphere decoder [11].…”
Section: Introductionmentioning
confidence: 99%
“…Hence, the resulting code, along with standard HLPL-constructs, it requires as well the utilization of compiler directives (e.g., pragmas inserted in the C/C++ code) which are necessary to help the HLS tool to produce an efficient RTL description (e.g., to force unrolling of loop-structures or to specify the specific FPGA resources that must be used to implement an array). When such low-level FPGA architectural design details are contemplated from the high-level description, then both the developmentcycle time and the design complexity of HLS-based flows are comparable to that of custom HDL code generation [26].…”
Section: Automated Hdl Generation and Schematic-entry Hdl-based Designmentioning
confidence: 99%