Implementation of Wave-Pipelined Interconnects in FPGAs

Mak, Terrence; D'Alessandro, C.; Sedcole, P.; Cheung, Peter Y. K.; Yakovlev, Alex; Luk, Wayne

doi:10.1109/nocs.2008.4492743

Cited by 4 publications

(3 citation statements)

References 3 publications

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“…Wave-pipelined interconnect for FPGAs was studied in [8,9]. That work, which does not include a reliability assessment or attempt to customize FPGA interconnect circuitry, predicts a throughput of 1.4Gbps at a length of 75 tiles (about 18 stages using our terminology) in a 65nm process.…”

Section: Related Workmentioning

confidence: 99%

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Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs

Teehan

Lemieux

Greenstreet

2009

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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FPGA user clocks are slow enough that only a fraction of the interconnect's bandwidth is actually used. There may be an opportunity to use throughput-oriented interconnect to decrease routing congestion and wire area using on-chip serial signaling, especially for datapath designs which operate on words instead of bits. To do so, these links must operate reliably at very high bit rates. We compare wave pipelining and surfing source-synchronous schemes in the presence of power supply and crosstalk noise. In particular, supply noise is a critical modeling challenge; better models are needed for FPGA power grids. Our results show that wave pipelining can operate at rates as high as 5Gbps for short links, but it is very sensitive to noise in longer links and must run much slower to be reliable. In contrast, surfing achieves a stable operating bit rate of 3Gbps and is relatively insensitive to noise.

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Section: Related Workmentioning

confidence: 99%

“…Figure 15 examines this penalty, showing the arrival time of the first bit as well as bits 8,16, and 32 relative to a regular interconnect wire. The regular interconnect wire follows the same circuit design as the wave-pipelined interconnect (shielded, 25x final driver, CMOS multiplexer), so it should be considered very fast.…”

Section: Latencymentioning

confidence: 99%

Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs

Teehan

Lemieux

Greenstreet

2009

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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“…FPGAs are increasingly used in modern parallel Filtering algorithm applications such as medical imaging (Leeser et al, 2005), Mapping DSP Algorithms (Maslennikow and Sergiyenko, 2006), image processing (Kiran, 2008), power consumption in portable image processing (Atabany, 2008), MPEG-4 motion estimation in mobile applications (Gao, 2003), satellite data processing (Nataraj et al, 2009), new Mersenne Number Transform (Nibouche et al, 2009), high speed wavelet-based image compression (Masoudnia et al, 2005) and even the global communication link (Mak et al, 2008). Most of the above FPGA-based solutions are typically programmed with hardware description languages (HDL) inherited from ASIC (Chang, 2005) and microprocessor-based DSP design methodologies (Aziz, 2004;Alshibami, 2001).…”

Section: Introductionmentioning

confidence: 99%

FPGA-Based Architecture for a Generalized Parallel 2-D MRI Filtering Algorithm

U.¹

2011

American Journal of Engineering and Applied Sciences

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Problem statement: Current Neuroimaging developments, in biological research and diagnostics, demand an edge-defined and noise-free MRI scans. Thus, this study presents a generalized parallel 2-D MRI filtering algorithm with their FPGA-based implementation in a single unified architecture. The parallel 2-D MRI filtering algorithms are Edge, Sobel X, Sobel Y, Sobel X-Y, Blur, Smooth, Sharpen, Gaussian and Beta (HYB). Then, the nine MRI image filtering algorithm, has empirically improved to generate enhanced MRI scans filtering results without significantly affecting the developed performance indices of high throughput and low power consumption at maximum operating frequency. Approach: The parallel 2-d MRI filtering algorithms are developed and FPGA implemented using Xilinx System Generator tool within the ISE 12.3 development suite. Two unified architectures are behaviorally developed, depending on the abstraction level of implementation. For performance indices comparison, two Virtex-6 FPGA boards, namely, xc6vlX240Tl-1lff1759 and xc6vlX130Tl-1lff1156 are behaviorally targeted. Results: The improved parallel 2-D filtering algorithms enhanced the filtered MRI scans to be edge-defined and noise free grayscale imaging. The single architecture is efficiently prototyped to achieve: high filtering performance of (11230 frames/second) throughput for 64*64 MRI grayscale scan, minimum power consumption of 0.86 Watt with a junction temperature of 52°C and a maximum frequency of up to (230 MHz). Conclusion: The improved parallel MRI filtering algorithms which are developed as a single unified architecture provide visibility enhancement within the filtered MRI scan to aid the physician in detecting brain diseases, e.g., trauma or intracranial haemorrhage. The high filtering throughput is feasibly nominee the nine parallel MRI filtering algorithms for applications such as real-time MRI potential future applications. Future Work: a set of parallel 3-D fMRI filtering algorithms will be investigated to be developed and fast FPGA prototyped for future research project

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