A mixed-signal VLSI chip architecture f o r multilayer feed-forward neural network implementation with digitally programmable synapses is presented. The chip realizes a fully connected single-layer network, configurable as a 48 input/48 output neurons with 2304 5-bit synapses or as a 24 anput/24 output neurons with 1152 9-bit synapses. This single layer network can be reconfigured as a multi-layer network. Another important chip feature is the possibility of connecting the chips in order to obtain a more complex multi-layer neural network. The core of our architecture is a very eficient circuit block, quoted as "Distributed Sigmoid-Synapse", that we used to implement each of the 2304 5-bit synapses included in the programmable neural network. A prototyping chip, including all the basic block of neural architecture, is now processed b y ES2 with 1.0 pm CMOS technology, Finally, we report the architecture of a possible setup system for the evaluation of the VLSI chip performances. Parameter mismatches present in the chip were considered to be not critical because it is possible to account them during the training of the neural network b y using a special chip-in-the-loop training algorithm. We planned to use this chip in pattern recognition and image processing applications.

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