VLSI implementation of a modular and programmable neural architecture

Abstract

A mixed-signal VLSI chip architecture f o r multilayer feed-forward neural network implementation with digitally programmable synapses is presented. The chip realizes a fully connected single-layer network, configurable as a 48 input/48 output neurons with 2304 5-bit synapses or as a 24 anput/24 output neurons with 1152 9-bit synapses. This single layer network can be reconfigured as a multi-layer network. Another important chip feature is the possibility of connecting the chips in order to obtain a more complex multi-layer neural network. The core of our architecture is a very eficient circuit block, quoted as "Distributed Sigmoid-Synapse", that we used to implement each of the 2304 5-bit synapses included in the programmable neural network. A prototyping chip, including all the basic block of neural architecture, is now processed b y ES2 with 1.0 pm CMOS technology, Finally, we report the architecture of a possible setup system for the evaluation of the VLSI chip performances. Parameter mismatches present in the chip were considered to be not critical because it is possible to account them during the training of the neural network b y using a special chip-in-the-loop training algorithm. We planned to use this chip in pattern recognition and image processing applications.

The simplicial neural cell and its mixed-signal circuit implementation: an efficient neural-network architecture for intelligent signal processing in portable multimedia applications

“…In fact, although the requirement of RAM cells is quite similar (as expected, since the same amount of knowledge should be stored), the simplicial neuron architecture leads to a dramatic reduction in the number of devices otherwise associated to the synapses and neurons of the equivalent MLP's or other type of neural network. [21] VIII. CONCLUDING REMARKS In this paper, a novel neural architecture exploiting the simplicial subdivision proposed in [3] for PWL approximation of nonlinear circuits was introduced.…”

“…Instead, the MLP in [21] requires additional wiring circuitry to accommodate a variable number of hidden nodes as required by a certain application. Also, while the RAM storage in the MLP is distributed in many registers of five bits each, one single compact RAM is used by the simplicial neuron thus making the silicon use more effective.…”

“…Since each synapse has to be programmed with five bits, a RAM of at least 166 5 803 bits is required to store the weights. In addition, the VLSI implementation of the MLP in [21] would require 166 synaptic circuits (each containing 24 MOS transistors) and 16 neuron units. It is obvious from Table III that the simplicial neuron require almost 63% of the RAM cells and less than 2.5% of the CMOS transistors required by the programmable MLP in [21] (assuming that ten CMOS transistors suffice to implement a comparator in the simplicial neuron).…”

“…A 9:15:1 structure results, i.e., 15 neurons on the hidden layer and a total of 150 16 166 synapses. In order to achieve programmability, the mixed-signal VLSI solution in [21] can be used to implement the MLP. Since each synapse has to be programmed with five bits, a RAM of at least 166 5 803 bits is required to store the weights.…”

A reconfigurable architecture for real-time digital simulation of neurons

“…Mixed-signal designs are either implemented as VLSI systems or a mixture of FPAAs and Field Programmable Gate Arrays (FPGAs). Cardaralli et al [7] use a hierarchical modular design with the perceptron model to build a multilayer feed forward network of neurons. These are built using a bespoke VLSI architecture using D/A and A/D to construct digitally programmed sigmoid synapses and neurons using the perceptron model.…”