Implementing P-Channel Junctionless Thin-Film Transistor on Poly-Ge<sub>0.95</sub>Sn<sub>0.05</sub> Film Formed by Amorphous GeSn Deposition and Annealing

Chou, Chuan-Pu; Lin, Yan-Xiao; Wu, Yung-Hsien

doi:10.1109/led.2018.2846882

Cited by 8 publications

(7 citation statements)

References 13 publications

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“…Data extracted are in accordance with previous results, where the carrier mobility increased as a function of Sn concentration due to the proportional increase in channel compressive strain and/or electronic structure variation such as the lower effective mass, which boosts the hole mobility; whereas, the major mobility limitations are the phonons and alloy scattering. Note that as expected in a structure like a nanowire with surfaces on all sides and consequently enhanced surface carrier scattering, the mobility values are lower than those extracted in thick films, which have minimal surface scattering effects. ,− …”

Section: Resultsmentioning

confidence: 72%

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Field-Effect Transistor Figures of Merit for Vapor–Liquid–Solid-Grown Ge_1-xSn_x (x = 0.03–0.09) Nanowire Devices

Galluccio

Doherty

Biswas

et al. 2020

ACS Appl. Electron. Mater.

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Ge1‑x Sn x alloys form a heterogeneous material system with high potential for applications in both optoelectronic and high-speed electronics devices. The attractiveness of Ge1‑x Sn x lies in the ability to tune the semiconductor band gap and electronic properties as a function of Sn concentration. Advances in Ge1‑x Sn x material synthesis have raised expectations recently, but there are considerable problems in terms of device demonstration. Although Ge1‑x Sn x thin films have been previously explored experimentally, in-depth studies of the electrical properties of Ge1‑x Sn x nanostructures are very limited, specifically those on nanowires grown via a bottom-up vapor–liquid–solid (VLS) process using metal catalysts. In this study, a detailed electrical investigation is presented of nominally undoped Ge1‑x Sn x bottom-up-grown nanowire devices with different Sn percentages (3–9 at. %). The entire device fabrication process is performed at relatively low temperatures, the maximum temperature being 440 °C. Device current modulation is performed through backgating from a substrate electrode, achieving impressive on–off current (I ON/I OFF) ratios of up to 104, showing their potential for electronic and sensor-based applications. Contact resistance (R C) extraction is essential for proper VLS-grown nanowire device electrical evaluation. Once the R C contribution is extracted and removed, parameter values such as mobility can change significantly, by up to 70% in this work. When benchmarked against other Ge1‑x Sn x electronic devices, the VLS-grown nanowire devices have potential in applications where a high I ON/I OFF ratio is important and where thermal budget and processing temperatures are required to be kept to minimum.

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Section: Resultsmentioning

confidence: 72%

“…Table and Figure show the comparison between the most common electrical parameters reported to date, with different device architectures and GeSn channel compositions considering process temperatures below 1000 °C. − …”

Section: Resultsmentioning

confidence: 99%

Field-Effect Transistor Figures of Merit for Vapor–Liquid–Solid-Grown Ge_1-xSn_x (x = 0.03–0.09) Nanowire Devices

Galluccio

Doherty

Biswas

et al. 2020

ACS Appl. Electron. Mater.

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“…Poly-Ge TFTs 4 recently have aroused significant interest because of their superior mobility and lower process temperature as compared to poly-Si. Recently, junctionless (JL) poly-GeSn pchannel TFTs, 5 the successor of poly-Ge TFTs, have manifested desirable I ON /I OFF ratio and mobility with a low thermal budget. In addition, n-channel GeSn devices have also been demonstrated, 6 making poly-GeSn TFTs a promising technology for monolithic 3D IC.…”

Section: ■ Introductionmentioning

confidence: 99%

Junctionless Poly-GeSn Ferroelectric Thin-Film Transistors with Improved Reliability by Interface Engineering for Neuromorphic Computing

Chou

Lin

Huang

et al. 2019

ACS Appl. Mater. Interfaces

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Ferroelectric HfZrO x (Fe-HZO) with a larger remnant polarization (P r) is achieved by using a poly-GeSn film as a channel material as compared with a poly-Ge film because of the lower thermal expansion that induces higher stress. Then two-stage interface engineering of junctionless poly-GeSn (Sn of ∼5.1%) ferroelectric thin-film transistors (Fe-TFTs) based on HZO was employed to improve the reliability characteristics. With stage I of NH3 plasma treatment on poly-GeSn and subsequent stage II of Ta2O5 interfacial layer growth, the interfacial quality between Fe-HZO and the poly-GeSn channel is greatly improved, which in turn enhances the reliability performance in terms of negligible P r degradation up to 106 cycles (±2.7 MV/1 ms) and 96% P r after a 10 year retention at 85 °C. Furthermore, to emulate the synapse plasticity of the human brain for neuromorphic computing, besides manifesting the capability of short-term plasticity, the devices also exhibit long-term plasticity with the characteristics of analog conductance (G) states of 80 levels (>6 bit), small linearity for potentiation and depression of −0.83 and 0.62, high symmetry, and moderate G max/G min of 9.6. By employing deep neural network, the neuromorphic system with poly-GeSn Fe-TFT synaptic devices achieves 91.4% pattern recognition accuracy. In addition, the learning algorithm of spike-timing-dependent plasticity based on spiking neural network is demonstrated as well. The results are promising for on-chip training, making it possible to implement neuromorphic computing by monolithic 3D ICs based on poly-GeSn Fe-TFTs.

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“…This is the reason why GeSn has been proposed for pMOS or pTFT. However, the reported GeSn pTFTs in the literature suffered from poor I ON /I OFF [26][27][28][29], which is due to the leakage current of the small energy bandgap. Table 2 displays the crucial TFT device parameters of various poly-GeSn TFTs [26][27][28][29].…”

Section: Resultsmentioning

confidence: 99%

“…However, the reported GeSn pTFTs in the literature suffered from poor I ON /I OFF [26][27][28][29], which is due to the leakage current of the small energy bandgap. Table 2 displays the crucial TFT device parameters of various poly-GeSn TFTs [26][27][28][29]. The remarkably high I ON /I OFF and relatively sharp SS are the advantages of this study.…”

Section: Resultsmentioning

confidence: 99%

Remarkably High-Performance Nanosheet GeSn Thin-Film Transistor

et al. 2022

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High-performance p-type thin-film transistors (pTFTs) are crucial for realizing low-power display-on-panel and monolithic three-dimensional integrated circuits. Unfortunately, it is difficult to achieve a high hole mobility of greater than 10 cm2/V·s, even for SnO TFTs with a unique single-hole band and a small hole effective mass. In this paper, we demonstrate a high-performance GeSn pTFT with a high field-effect hole mobility (μFE), of 41.8 cm2/V·s; a sharp turn-on subthreshold slope (SS), of 311 mV/dec, for low-voltage operation; and a large on-current/off-current (ION/IOFF) value, of 8.9 × 106. This remarkably high ION/IOFF is achieved using an ultra-thin nanosheet GeSn, with a thickness of only 7 nm. Although an even higher hole mobility (103.8 cm2/V·s) was obtained with a thicker GeSn channel, the IOFF increased rapidly and the poor ION/IOFF (75) was unsuitable for transistor applications. The high mobility is due to the small hole effective mass of GeSn, which is supported by first-principles electronic structure calculations.

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Implementing P-Channel Junctionless Thin-Film Transistor on Poly-Ge_0.95Sn_0.05 Film Formed by Amorphous GeSn Deposition and Annealing

Cited by 8 publications

References 13 publications

Field-Effect Transistor Figures of Merit for Vapor–Liquid–Solid-Grown Ge_1-xSn_x (x = 0.03–0.09) Nanowire Devices

Field-Effect Transistor Figures of Merit for Vapor–Liquid–Solid-Grown Ge_1-xSn_x (x = 0.03–0.09) Nanowire Devices

Junctionless Poly-GeSn Ferroelectric Thin-Film Transistors with Improved Reliability by Interface Engineering for Neuromorphic Computing

Remarkably High-Performance Nanosheet GeSn Thin-Film Transistor

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Implementing P-Channel Junctionless Thin-Film Transistor on Poly-Ge0.95Sn0.05 Film Formed by Amorphous GeSn Deposition and Annealing

Cited by 8 publications

References 13 publications

Field-Effect Transistor Figures of Merit for Vapor–Liquid–Solid-Grown Ge1-xSnx (x = 0.03–0.09) Nanowire Devices

Field-Effect Transistor Figures of Merit for Vapor–Liquid–Solid-Grown Ge1-xSnx (x = 0.03–0.09) Nanowire Devices

Junctionless Poly-GeSn Ferroelectric Thin-Film Transistors with Improved Reliability by Interface Engineering for Neuromorphic Computing

Remarkably High-Performance Nanosheet GeSn Thin-Film Transistor

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Product

Resources

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Implementing P-Channel Junctionless Thin-Film Transistor on Poly-Ge_0.95Sn_0.05 Film Formed by Amorphous GeSn Deposition and Annealing

Field-Effect Transistor Figures of Merit for Vapor–Liquid–Solid-Grown Ge_1-xSn_x (x = 0.03–0.09) Nanowire Devices

Field-Effect Transistor Figures of Merit for Vapor–Liquid–Solid-Grown Ge_1-xSn_x (x = 0.03–0.09) Nanowire Devices