Defect detection plays a critical role in thin film transistor liquid crystal display (TFT-LCD) manufacturing. This paper proposes an inline defect-detection (IDD) system, by which the defects can be automatically detected in a TFT array process. The IDD system is composed of three stages: the image preprocessing, the appearance-based classification and the decision-making stages. In the first stage, the pixels can be segmented from an input image based on the designed pixel segmentation method. The pixels are then sent into the appearance-based classification stage for defect and non-defect classification. Two novel methods are embedded in this stage: the locally linear embedding (LLE) and the support vector data description (SVDD). LLE is able to substantially reduce the dimensions of the input pixels by manifold learning and SVDD is able to effectively discriminate the normal pixels from the defective ones with a hypersphere by one-class classification. After aggregating the classification results, the third stage outputs the final detection result. Experimental results, carried out on real images provided by a LCD manufacturer, show that the IDD system can not only achieve a high defect-detection rate of over 98%, but also accomplish the task of inline defect detection within 4 s for one input image.

Ferroelectric HfZrO x (Fe-HZO) with a larger remnant polarization (P r) is achieved by using a poly-GeSn film as a channel material as compared with a poly-Ge film because of the lower thermal expansion that induces higher stress. Then two-stage interface engineering of junctionless poly-GeSn (Sn of ∼5.1%) ferroelectric thin-film transistors (Fe-TFTs) based on HZO was employed to improve the reliability characteristics. With stage I of NH3 plasma treatment on poly-GeSn and subsequent stage II of Ta2O5 interfacial layer growth, the interfacial quality between Fe-HZO and the poly-GeSn channel is greatly improved, which in turn enhances the reliability performance in terms of negligible P r degradation up to 106 cycles (±2.7 MV/1 ms) and 96% P r after a 10 year retention at 85 °C. Furthermore, to emulate the synapse plasticity of the human brain for neuromorphic computing, besides manifesting the capability of short-term plasticity, the devices also exhibit long-term plasticity with the characteristics of analog conductance (G) states of 80 levels (>6 bit), small linearity for potentiation and depression of −0.83 and 0.62, high symmetry, and moderate G max/G min of 9.6. By employing deep neural network, the neuromorphic system with poly-GeSn Fe-TFT synaptic devices achieves 91.4% pattern recognition accuracy. In addition, the learning algorithm of spike-timing-dependent plasticity based on spiking neural network is demonstrated as well. The results are promising for on-chip training, making it possible to implement neuromorphic computing by monolithic 3D ICs based on poly-GeSn Fe-TFTs.

No abstract

No abstract

No abstract