Implementing Synaptic Plasticity in a VLSI Spiking Neural Network Model

Schemmel, Johannes; Grübl, Andreas; Meier, K.; Mueller, E.

doi:10.1109/ijcnn.2006.246651

Cited by 58 publications

(26 citation statements)

References 14 publications

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“…Table 1 shows the structure presented in this paper results in the best synaptic density over other ICs built to date (Indiveri et al, 2006; Schemmel et al, 2006, 2008b; Camilleri et al, 2007; Brink et al, 2012). We define synapse density as the synapse area normalized by the square of the process node.…”

Section: Large-scale Neuromorphic Systemsmentioning

confidence: 88%

Finding a roadmap to achieve large neuromorphic hardware systems

2013

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Neuromorphic systems are gaining increasing importance in an era where CMOS digital computing techniques are reaching physical limits. These silicon systems mimic extremely energy efficient neural computing structures, potentially both for solving engineering applications as well as understanding neural computation. Toward this end, the authors provide a glimpse at what the technology evolution roadmap looks like for these systems so that Neuromorphic engineers may gain the same benefit of anticipation and foresight that IC designers gained from Moore's law many years ago. Scaling of energy efficiency, performance, and size will be discussed as well as how the implementation and application space of Neuromorphic systems are expected to evolve over time.

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Section: Large-scale Neuromorphic Systemsmentioning

confidence: 88%

Finding a roadmap to achieve large neuromorphic hardware systems

2013

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“…Together with on-chip bias-generation circuits such a model can be calibrated to quantitatively reproduce numerical simulations. Figure 17A shows an exemplary neuron circuit which is part of a 100k synapse network chip (Schemmel et al, 2006). The neuron emulates three ion-channels and a spike-generation circuit consisting of a high-speed comparator using positive feedback and an adjustable refractory period.…”

Section: Silicon Neuron Implementationsmentioning

confidence: 99%

Neuromorphic Silicon Neuron Circuits

Indiveri¹,

Linares-Barranco²,

Hamilton³

et al. 2011

Front. Neurosci

1,174

835

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Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

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“…The hard upper bound in network size (given by the number of available components on the neuromorphic device) can be broken by scaling of the devices themselves, e.g., by wafer-scale integration (Schemmel et al, 2010) or massively interconnected chips (Merolla et al, 2011). Emulations can be further accelerated by scaling down time constants compared to biology, which is enabled by deep submicron technology (Schemmel et al, 2006, 2010; Brüderle et al, 2011). Unlike high-throughput computing with accelerated systems, real-time systems are often specialized for low power operation (e.g., Farquhar and Hasler, 2005; Indiveri et al, 2006).…”

Section: Introductionmentioning

confidence: 99%

“…Apart from almost arbitrary network topologies, this system provides a vast configuration space for neuron and synapse parameters (Schemmel et al, 2006; Brüderle et al, 2011). Reconfiguration is achieved on-chip and does not require additional support hardware.…”

Section: Introductionmentioning

confidence: 99%

Six Networks on a Universal Neuromorphic Computing Substrate

Pfeil¹,

Grübl²,

Jeltsch³

et al. 2013

Front. Neurosci.

160

155

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In this study, we present a highly configurable neuromorphic computing substrate and use it for emulating several types of neural networks. At the heart of this system lies a mixed-signal chip, with analog implementations of neurons and synapses and digital transmission of action potentials. Major advantages of this emulation device, which has been explicitly designed as a universal neural network emulator, are its inherent parallelism and high acceleration factor compared to conventional computers. Its configurability allows the realization of almost arbitrary network topologies and the use of widely varied neuronal and synaptic parameters. Fixed-pattern noise inherent to analog circuitry is reduced by calibration routines. An integrated development environment allows neuroscientists to operate the device without any prior knowledge of neuromorphic circuit design. As a showcase for the capabilities of the system, we describe the successful emulation of six different neural networks which cover a broad spectrum of both structure and functionality.

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Implementing Synaptic Plasticity in a VLSI Spiking Neural Network Model

Cited by 58 publications

References 14 publications

Finding a roadmap to achieve large neuromorphic hardware systems

Finding a roadmap to achieve large neuromorphic hardware systems

Neuromorphic Silicon Neuron Circuits

Six Networks on a Universal Neuromorphic Computing Substrate

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