Implications of Device Timing Variability on Full Chip Timing

Abstract

As process technologies continue to scale, the magnitude of within-die device parameter variations is expected to increase and may lead to significant timing variability. This paper presents a quantitative evaluation of how low level device timing variations impact the timing at the functional block level. We evaluate two types of timing variations: random and systematic variations. The study introduces random and systematic timing variations to several functional blocks in Intel® Core™ Duo microprocessor design database and measures the resulting timing margins. The primary conclusion of this research is that as a result of combining two probability distributions (the distribution of the random variation and the distribution of path timing margins) functional block timing margins degrade non-linearly with increasing variability.

Resilient Architecture Design for Voltage Variation

“…circuit-level techniques must be applied carefully to all the critical executions paths for timing violations. Annavaram et al showed that the distribution of timing margins for different paths across functional blocks in the Intel Core Duo microprocessor have hundreds of paths within 10% timing margins [5]. Designs such as Razor impact overall processor performance and area overhead, as well as design and verification effort.…”

DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors

“…However, Razor may be costly to implement in a high-performance out-of-order core with several large array structures and tight timing paths. A recent study by Annavaram et al [3] shows the distribution of timing margins for different paths across functional blocks in the Intel Core Duo microprocessor have hundreds of paths within 10% timing margins. This suggests that voltage-induced violations are likely to affect many paths.…”