Resilient Architecture Design for Voltage Variation

Abstract

Shrinking feature size and diminishing supply voltage are making circuits sensitive to supply voltage fluctuations within the microprocessor, caused by normal workload activity changes. If left unattended, voltage fluctuations can lead to timing violations or even transistor lifetime issues that degrade processor robustness. Mechanisms that learn to tolerate, avoid, and eliminate voltage fluctuations based on program and microarchitectural events can help steer the processor clear of danger, thus enabling tighter voltage margins that improve performance or lower power consumption. We describe the problem of voltage variation and the factors that influence this variation during processor design and operation. We also describe a variety of runtime hardware and software mitigation techniques that either tolerate, avoid, and/or eliminate voltage violations. We hope processor architects will find the information useful since tolerance, avoidance, and elimination are generalizable constructs that can serve as a basis for addressing other reliability challenges as well.

b-HiVE

“…However, the impact of these techniques is hampered by the traditional worst-case design of systems. Advanced technology scaling leads to a probabilistic behavior in CMOS [1], forcing designers to add significant voltage margins and timing slack [13] to overcome the environmental fluctuations and design uncertainties. The resulting conservative guard-bands reduce both performance and power efficiency.…”