Implications of Small Geometry Effects on &lt;inline-formula&gt; 
                     &lt;tex-math notation="LaTeX"&gt;$g_m/I_D$ &lt;/tex-math&gt;
                  &lt;/inline-formula&gt; Based Design Methodology for Analog Circuits

Ou, Jack; Ferreira, Pietro Maris

doi:10.1109/tcsii.2018.2846484

Cited by 15 publications

(4 citation statements)

References 15 publications

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“…W F is ∼450 nm for an NMOS device in the target technology. This shift in V th is caused by the fringing capacitances between the gate, side-wall and active area [21]. Similar observations can be made for PMOS devices where in both cases, DIBL and BDE are unfavorable for exploiting V th for performance.…”

Section: Impact Of Short Channel Effects On Devicessupporting

confidence: 60%

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MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-$V_{th}$ Computing

Ranasinghe

Gerez

2020

2020 IEEE 38th International Conference on Computer Design (ICCD)

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This paper presents an energy-efficient standardcell library design scheme: MEPNTC, targeting ultra-low-voltage near/sub-V th operation. MEPNTC exploits an alternative logic style and inverse-narrow-width-effect (INWE) to extend the minimum energy point operation. A carefully engineered design style is presented to improve the PVT and glitch immunity of the cells while preserving balanced noise margins across a wider VDD range. The reduced parasitics and performance boost from both techniques have demonstrated up to 30%-60% of energy savings at 0.5V, typical near-V th level for general-purpose hardware accelerator benchmarks (32-bit Booth Multiplier, 25-Tap FIR Filter, Forward Discrete Cosine Transform and JPEG Image Compression Units) compared to standard CMOS and INWE aware CMOS designs in 65-nm bulk CMOS technology.

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Section: Impact Of Short Channel Effects On Devicessupporting

confidence: 60%

“…As depicted, V th is no longer stable due to SCEs and therefore its impact on near/sub-V th regions could be undesirable, ascribed to the exponential dependency of V th on the drain current. The relationship of these terms to the on-current of the device can be formulated as follows [11], [19]- [21]:…”

Section: Impact Of Short Channel Effects On Devicesmentioning

confidence: 99%

MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-$V_{th}$ Computing

Ranasinghe

Gerez

2020

2020 IEEE 38th International Conference on Computer Design (ICCD)

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“…7 shows that C 1 (W ) changes significantly with a factor of 2.12 between small (0.135 μm) and large geometries (1.35 μm). This illustrates the impact of small geometries on the constants V th and n, studied in [17]. Dissipative phenomena are put in evidence for small width.…”

Section: B F (W X) Pls Results For a Single Dendritementioning

confidence: 73%

Revisiting the Ultra-Low Power Electronic Neuron Towards a Faithful Biomimetic Behavior

Rioufol,

Jouni,

Soupizet

et al. 2023

2023 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)

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The spiking neural networks (SNN) have been considered as the third generation of neural networks, since it better mimics the biological behavior of the brain cortex which processes spike trains. This paper proposes to revisit electronic neuron implementations in a novel way able to deal with SNN limitations in deep learning. Post-layout simulation results prove that non-linear action function is able to shift from right to left considering a reference sizing to create excitation and inhibition synaptic current. Proposed model is extended to handle up to three neurons in a parallel association, i.e. SNN with a fanin/fan out of 3 synaptic branches. Revisited electronic neuron achieves an area of 10.8 × 9.7 μm 2 for a energy efficiency below 10 fJ/spike, while including synapse circuitry. Relative standard deviation of synapse current is below 1.8% and synapses weight mismatch leads to less than 4 pA current error.

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“…In addition, the NF dependence was not addressed. In [14], a unit-sized transistor was used with with specific dimensions such that the impact of LDEs is minor. However, this approach assumes that any device must be an integer multiple of the unit-sized device, which deprives the designer from the flexibility of setting N F and W F according to the design requirements.…”

Section: Introductionmentioning

confidence: 99%

Capturing Layout Dependent Effects in MOSFET Circuit Sizing Using Precomputed Lookup Tables

et al. 2023

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Sizing analog circuits using precomputed look-up tables (LUTs) has recently gained traction for fast and systematic design-space exploration without a simulator in the loop. In its current form, the underlying g m /I D -based design methodology assumes that the MOSFET figures of merit are independent of absolute channel width. However, this assumption can introduce significant errors when the layoutdependent effects (LDEs) of modern CMOS technologies are considered. In this paper, an accurate and efficient procedure is developed that incorporates the dependence on the MOSFET width per finger and number of fingers in the precomputed LUTs. The proposed approach uses a set of normalized auxiliary LUTs to correct the device behavior with a subtle impact on the LUT size and the computational effort. Moreover, the nonlinear variation of the drain-to-bulk (c db ) and source-to-bulk (c sb ) capacitances with the device number of fingers is taken into account. The correction is based on precomputed simulation data and is thus independent of the model parameters and implementation. We present a track-and-hold circuit example that is sensitive to the width independence assumption, and show that the proposed fix prevents overdesign, resulting in a 44% reduction in switch area.INDEX TERMS gm/ID methodology, precomputed lookup tables, analog design automation, layout dependent effects (LDEs)

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Implications of Small Geometry Effects on <inline-formula> <tex-math notation="LaTeX">$g_m/I_D$ </tex-math> </inline-formula> Based Design Methodology for Analog Circuits

Cited by 15 publications

References 15 publications

MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-$V_{th}$ Computing

MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-$V_{th}$ Computing

Revisiting the Ultra-Low Power Electronic Neuron Towards a Faithful Biomimetic Behavior

Capturing Layout Dependent Effects in MOSFET Circuit Sizing Using Precomputed Lookup Tables

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