Imprint lithography for integrated circuit fabrication

Abstract

The escalating cost for next generation lithography (NGL) tools is driven in part by the need for complex sources and optics. The cost for a single NGL tool could exceed $50M in the next few years, a prohibitive number for many companies. As a result, several researchers are looking at low cost alternative methods for printing sub-100 nm features. In the mid-1990’s, several research groups started investigating different methods for imprinting small features. Many of these methods, although very effective at printing small features across an entire wafer, are limited in their ability to do precise overlay. In 1999, Colburn et al. [Proc. SPIE 379 (1999)] discovered that imprinting could be done at low pressures and at room temperatures by using low viscosity UV curable monomers. The technology is typically referred to as step and flash imprint lithography. The use of a quartz template enabled the photocuring process to occur and also opened up the potential for optical alignment of the wafer and template. This article traces the development of nanoimprint lithography and addresses the issues that must be solved if this type of technology is to be applied to high-density silicon integrated circuitry.

High Temporal Resolution Measurements of Shrinkage Characteristics of UV Nanoimprint Rresin

“…Figure 7 shows a comparison of the shrinkage variation with UV exposure time with the polymerization rate variation fitted using the first-order reaction kinetics. We can find that the shrinkage variation can be fitted very well with the first-order reaction kinetics given by Equation (2). This means that the shrinkage variation induced with UV exposure was in good agreement with the polymerization rate suggested as the first-order reaction kinetics of polymerization.…”

Defect-Tolerant CMOL Cell Assignment via Satisfiability

“…In recent years, nanoelectronics has made tremendous progress, with advances in novel nanodevices [18], nanocircuits [1,5], nano-crossbar arrays [2,8,12], manufacture by nanoimprint lithography [10,19], CMOS/nano co-design architectures [3,9,20], and applications [15][16][17]. Although a two-terminal nanowire crossbar array does not have the functionality of FET-based circuits, it has the potential for incredible density and low fabrication costs [9].…”

Effect of Equilibrium Contact Angle on Drainage Property at Microperiodic Structure with Staggered Pillar Array

“…Finally, the photoresist was removed using a piranha solution, which is a mixture of sulfuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 O 2 ), after which the remaining SiO 2 was removed using hydrogen fluoride (HF). An ultraviolet (UV) nanoimprint technique (19,20) . Positive-patterned test pieces with periodic structures were transferred from the negative-patterned master mold.…”