Improved Design of High-Performance Parallel Decimal Multipliers

Vázquez, Álvaro; Antelo, E.; Montuschi, Paolo

doi:10.1109/tc.2009.167

Cited by 85 publications

(58 citation statements)

References 24 publications

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“…DPD designs started first by presenting ideas for carry-save addition for decimal fixed point multipliers [37] then iterative high-frequency multipliers [38] and multioperand addition [39]. That early work combined with partial product generation [40] formed the base for the complete floating point multipliers [41,42] and the innovative ideas [33] relying on the various decimal codes yielding fully parallel floating point multipliers [13,34].…”

Section: Specific Designsmentioning

confidence: 99%

Decimal Floating Point Number System

Fahmy

2017

Embedded Systems Design With Special Arithmetic and Number Systems

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Section: Specific Designsmentioning

confidence: 99%

Decimal Floating Point Number System

Fahmy

2017

Embedded Systems Design With Special Arithmetic and Number Systems

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“…Nonetheless, the recently commercialized digital processors contain radix-10 sequential multipliers with more efficient PPG [5], as well as decimal division units [25], all implemented by binary logical circuits. Fast parallel decimal multiplication [10,15,27], high-speed decimal division [17,20], and even decimal CORDIC [18], which are also optimized for condensed silicon area and/or reduced power dissipation, have been recently reported.…”

Section: Introductionmentioning

confidence: 99%

“…The general trend in the design and implementation of radix-10 multipliers (sequential or parallel) is to develop the PPG part based on the selection of pre-computed decimal multiples of the multiplicand, where many relevant proposals have appeared in the literature with a wide spectrum of area/speed tradeoff (e.g., [10,15,19,27]). However, the PPG part of one recent FPGA implementation of decimal multiplication [26] has used the 1×1 binary-coded decimal (BCD) digit multiplier that was presented in [14].…”

Section: Introductionmentioning

confidence: 99%

Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers

Gorgin

Jaberipur

Asl

2014

Circuits Syst Signal Process

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Partial product generation (PPG), in radix-10 multiplication hardware, is often done through selection of pre-computed decimal multiples of the multiplicand. However, ASIC and FPGA realization of classical PPG via digit-by-digit multiplication has recently attracted some researchers. For example, a sequential multiplier, squarer, divider, FPGA parallel multiplier, and array multiplier are all based on a specific binary-coded decimal (BCD) digit multiplier (BDM). Most BDMs, as we have encountered, compute the binary product of two 1-digit BCD operands, and convert it to 2-digit BCD product. We provide our own version of two of these works with some adjustments and improvements, and offer two new low-cost BDMs in this category. However, a recent FPGA BDM uses straightforward truth table approach from scratch and skips binary product generation. We redesign the latter via low-level FPGA programming, and also provide its ASIC realization. We synthesize all the studied and new designs on ASIC and FPGA platforms, exhaustively check them for correctness, and compare their performance, to show that our two new designs, and the ASIC and new FPGA realizations of the aforementioned fully truth table-based design, outperform the previous ones in terms of one or more figures of merit.

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“…1, adapted from [2]. In this Figure, the PPG mostly consists of wired shifts and various recoders the same as in [2].…”

mentioning

confidence: 99%

“…However, we decided on generating the 4X directly from X, not by cascading two 2X blocks, so as to manage to perform PPG in one cycle. Consequently, the area of the proposed PPG is slightly higher than the previous counterpart [2]. The next step after computing the easy multiples is to select values for U i , V i ∈ {0, X, 2X, 4X, 5X}, regarding y i : y 3 i y 2 i y 1 i y 0 i , so as to generate the ith partial product P i = U i + V i .…”

mentioning

confidence: 99%

Improved design of high‐frequency sequential decimal multipliers

Kaivani

Liu

2014

Electron. lett.

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Hardware implementation of decimal arithmetic operations has become a hot topic for research during the last decade. Among various operations, decimal multiplication is considered as one of the most complicated dyadic operations, which requires high-cost hardware implementation. Therefore, the processor industry has opted to use the sequential decimal multipliers to reduce the high cost of parallel architectures. However, the main drawback of iterative multipliers is their high latency. In this reported work, the focus has been on reducing the latency of decimal sequential multipliers while maintaining a low cost of area. Consequently, a high-frequency sequential decimal multiplier is proposed whose cycle time is reduced to the latency of a binary half-adder plus that of a decimal multiply-by-two operation, which overall is less than that of a decimal carry-save adder. The synthesis results reveal that the proposed sequential multiplier works with a higher clock frequency than the fastest previous decimal multiplier which in turn leads to overall latency advantage.Introduction: Hardware implementation of decimal floating-point arithmetic has been gaining revived popularity during the last decade. However, the complexity of the decimal number system brings about more challenges to be dealt with during the hardware implementation, compared with the binary counterparts. With the intention to reduce the high cost of these decimal operations the processor industry has opted for sequential realisation [1]. However, sequential hardware realisation is at a disadvantage because of its high latency.This Letter focuses on the hardware realisation of the decimal multiplication and a novel architecture is proposed to ameliorate the problem of slow sequential decimal multipliers via increasing the clock frequency. In this design, the cycle time is reduced to the latency of a binary half-adder (HA) plus that of a decimal multiply-by-two operation, which overall is less than that of a decimal carry-save adder (CSA). The claimed improvement is supported by synthesising and comparing the proposed design to those of the best previous pertinent works.The proposed design includes the following novelties, with respect to previous works:

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Improved Design of High-Performance Parallel Decimal Multipliers

Cited by 85 publications

References 24 publications

Decimal Floating Point Number System

Decimal Floating Point Number System

Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers

Improved design of high‐frequency sequential decimal multipliers

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