Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits

Ali, S.; Li, Ké; Wilcock, R.; Wilson, P.

doi:10.1109/date.2009.5090757

Cited by 5 publications

(4 citation statements)

References 10 publications

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“…The authors also adopted the linear VCO model which may be sufficient for performing verification on fixed designs, but is overoptimistic for design exploration since the VCO linearity condition is not always valid. The VCO behavioral models developed in [42,43] used lookup-tables (LUTs) inside Verilog-A modules. LUTs only hold a limited number of simulated sample points.…”

Section: Related Prior Researchmentioning

confidence: 99%

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

Mohanty,

Kougianos

2019

Preprint

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Electronic circuit behavioral models built with hardware description/modeling languages such as Verilog-AMS for system-level simulations are typically functional models. They do not capture the physical design (layout) information of the target design. Thus, their applications are limited to early design feasibility studies and/or pre-layout functional verification. Numerous iterations of post-layout design adjustments are usually required to ensure that design specifications are met with the presence of layout parasitics. In this paper a paradigm shift of the current trend is presented that integrates layout-level information (with full parasitics) in Verilog-AMS through metamodels such that systemlevel simulation of a mixed-signal circuit/system is realistic and as accurate as true parasitic netlist simulation. The simulations performed with these parasitic-aware models can be used to estimate system performance without layout iterations. We call this new form of Verilog-AMS as iVAMS (i.e. Intelligent Verilog-AMS). We call this iVAMS 1.0 as it is simple polynomial-metamodel integrated Intelligent Verilog-AMS. As a specific case study, a voltage-controlled oscillator (VCO) Verilog-AMS behavioral model and design flow are proposed to assist fast PLL design space exploration. The PLL simulation employing quadratic metamodels achieves approximately 10× speedup compared to that employing the layout extracted, parasitic netlist. The simulations using this behavioral model attain high accuracy. The observed error for the simulated lock time and average power dissipation are 0.7 % and 3 %, respectively. This behavioral metamodel approach bridges the gap between layout-accurate but fast simulation and design space exploration. The proposed method also allows much shorter design verification and optimization to meet stringent time-to-market requirements. In the PLL optimization case study, 46 % PLL power reduction was achieved using a differential evolution algorithm and the proposed layout-accurate behavioral model. Compared to the optimization using the layout netlist, the runtime using the behavioral model is reduced by 88.9 %. To the best of the authors' knowledge this is the first approach that brings layout-level accuracy to system-level design exploration and is applied towards mixed-signal design exploration.

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Section: Related Prior Researchmentioning

confidence: 99%

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

Mohanty,

Kougianos

2019

Preprint

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“…In the case of CMOS transistor designs, optimising device sizes and selecting appropriate topologies are methods used to tackle variability [4][5][6]. The greatest workload and responsibility remains to date with chip manufacturers, who continuously improve fabrication facilities and feed-back appropriate design rules for creating the physical layout to the designers in order to ensure high yield figures.…”

Section: Background and Rationalementioning

confidence: 99%

“…The results in [4,26], which have been obtained from statistical SPICE simulations, suggest that optimising the widths of transistors in standard cells can improve their variability tolerance, speed and power consumption. It is also shown that it is possible to design and optimise analogue CMOS circuits in hardware using field programmable transistor arrays (FPTAs) [12,27], and there are examples where transistor-level reconfiguration is used as a mechanism for design optimisation [5,6]. Therefore if FPTA-based mechanisms to alter device sizes are incorporated in a hardware architecture, it will be possible to optimise circuit designs post-fabrication, that is, adapt them in such a way that they perform optimally on the silicon die they are fabricated on.…”

Section: Design Optimisation Via Transistor Sizingmentioning

confidence: 99%

Fighting stochastic variability in a D‐type flip‐flop with transistor‐level reconfiguration

Trefzer¹,

Walker²,

Bale³

et al. 2015

IET Computers & Digital Techniques

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In this study, the authors present a design optimisation case study of D-type flip-flop timing characteristics that are degraded as a result of intrinsic stochastic variability in a 25 nm technology process. What makes this work unique is that the design is mapped onto a multi-reconfigurable architecture, which is, like a field programmable gate array (FPGA), configurable at the gate level but can then be optimised using transistor level configuration options that are additionally built into the architecture. While a hardware VLSI prototype of this architecture is currently being fabricated, the results presented here are obtained from a virtual prototype implemented in SPICE using statistically enhanced 25 nm high performance metal gate MOSFET compact models from gold standard simulations for pre-fabrication verification. A Dtype flip-flop is chosen as a benchmark in this study, and it is shown that timing characteristics that are degraded because of stochastic variability can be recovered and improved. This study highlights significant potential of the programmable analogue and digital array architecture to represent a next-generation FPGA architecture that can recover yield using post-fabrication transistor-level optimisation in addition to adjusting the operating point of mapped designs.

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“…The authors also adopted the linear VCO model which may be sufficient for performing verification on fixed designs, but is not useful for design exploration since the VCO linearity condition is not always valid. The VCO behavioral models developed in [1] and [6] use a tablelookup approach inside Verilog-A modules, which is not efficient for global design space exploration. An event-driven analog modeling approach was proposed in [13] which used the Verilog-AMS wreal data type to improve the model efficiency.…”

Section: Related Prior Researchmentioning

confidence: 99%

Verilog-AMS-PAM

Geng

Mohanty

Kougianos

et al. 2012

Proceedings of the Great Lakes Symposium on VLSI

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Current Verilog-AMS system level modeling does not capture the physical design (layout) information of the target design as it is meant to be fast behavioral simulation only. Thus, the results of behavioral simulation can be very inaccurate. In this paper a paradigm shift of the current trend is presented that integrates layout level information (with full parasitics) in Verilog-AMS through polynomial metamodels such that system-level simulation of a mixedsignal circuit/system is realistic and as accurate as the true parasitic netlist simulation. As a specific case study, a voltage-controlled oscillator (VCO) Verilog-AMS behavioral model and design flow are proposed to assist fast PLL design exploration. Based on a quadratic polynomial metamodel, the PLL simulation achieves approximately a 10× speedup compared to the layout extracted, parasitic netlist. The simulations using this behavioral model attain high accuracy. The observed error for the simulated lock time and average power consumption are 0.7 % and 3 %, respectively. This behavioral metamodel approach bridges the gap between layout accurate but fast simulation and design space exploration.

show abstract

Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits

Cited by 5 publications

References 10 publications

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

Fighting stochastic variability in a D‐type flip‐flop with transistor‐level reconfiguration

Verilog-AMS-PAM

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