Improved structure for efficient charge recoverylogic

Liu, F.; Lau, K.T.

doi:10.1049/el:19981210

Cited by 13 publications

(7 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In other comparative studies (Moon and Jeong 1996, Oklobdẑ zija et al 1997, Liu and Lau 1998a, b, Kim and Papaefthymiou 1998 where PFAL was not taken into consideration, IECRL and PAL were shown to be the best adiabatic circuits. Since we have now shown that PFAL is better than these two other solutions, it is possible to conclude that, at least for dual-rail¯ip-¯op adiabatic logic circuits, the PFAL logic circuit seems to represent the most attractive alternative.…”

Section: Results and Conclusionmentioning

confidence: 87%

A comparison of some circuit schemes for semi-reversible adiabatic logic

Blotti¹,

Pascoli²,

Saletti³

2002

International Journal of Electronics

View full text Add to dashboard Cite

Four flip-flop-like adiabatic logic circuits, suited for a standard cell library implementation, were compared in terms of absolute energy consumption and effectiveness of adiabatic energy recovery. The energy performance of ECRL, IECRL, PAL and PFAL logic circuits was determined, by means of SPICE simulation, as a function of capacitive load and operational frequency. The comparison showed that the PFAL circuit is the best flip-flop-based adiabatic solution as far as power consumption is concerned

show abstract

Section: Results and Conclusionmentioning

confidence: 87%

A comparison of some circuit schemes for semi-reversible adiabatic logic

Blotti¹,

Pascoli²,

Saletti³

2002

International Journal of Electronics

View full text Add to dashboard Cite

show abstract

“…If outputs are used as internal control signals, i.e. if c 1 = ϕ 1 and c 2 = ϕ 2 , the circuit complexity and occupied area are reduced, but also the conversion efficiency decreases (Liu and Lau, 1998).…”

Section: Overview Of Adiabatic Oscillatorsmentioning

confidence: 99%

“…In this paper, a high efficiency power supply generator is presented, which can be used for logic circuits implemented using three adiabatic families, namely ECRL Jeong, 1996, 1998), PFAL (Vetuli et al, 1996;Blotti et al, 2000), and 2N-2N2P (Kramer et al, 1995;Liu and Lau, 1998). These families require, as power supplies, four trapezoidal waveforms equally spaced in phase.…”

Section: Introductionmentioning

confidence: 99%

Resonant 90 degree shifter generator for 4-phase trapezoidal adiabatic logic

et al. 2003

View full text Add to dashboard Cite

Abstract. Many adiabatic logic families make use of multi phase trapezoidal or sinusoidal power clocks to recover the energy stored in the load capacitances. A key aspect for the evaluation of the performance of adiabatic logic is then the study of a system that includes the power clock generator. A four-phase trapezoidal power clock generator, according to the requirements of the most promising architectures, namely the ECRL and PFAL, has been designed and simulated. The proposed circuit, realized with a double-well 0.25 µm CMOS technology and external inductors, is a resonant generator designed to oscillate at a frequency of 7 MHz, which is within the optimum frequency range for adiabatic circuits realized with this CMOS technology. The generator has been simulated with the equivalent load of fifty 1-bit adders and the operating behavior of a 4-bit adder has been evaluated. The key aspects of a generator for adiabatic logic are its power consumption and the phase relationships between its output signals. The proposed generator has a conversion efficiency higher than 80%, and it is robust with respect to variations of technology parameters. The four power supplies exhibit the correct relationship of phase also in the presence of no equally distributed loads.

show abstract

“…It is also called 2N-2N2P logic [5]. The Basic operation and working of IECRL are described in [6], [7]. The IECRL resettable buffer circuit is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers

Maheshwari

Bartlett

Kale

2017

2017 European Conference on Circuit Theory and Design (ECCTD)

View full text Add to dashboard Cite

obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/).In case of abuse or copyright appearing without permission e-mail repository@westminster.ac.uk

show abstract

Improved structure for efficient charge recoverylogic

Cited by 13 publications

References 4 publications

A comparison of some circuit schemes for semi-reversible adiabatic logic

A comparison of some circuit schemes for semi-reversible adiabatic logic

Resonant 90 degree shifter generator for 4-phase trapezoidal adiabatic logic

Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers

Contact Info

Product

Resources

About