“…5,6 Although the implementation of both low and high-k dielectric materials by the industry has enabled impressive gains in device performance and the continuation of Moore's law, 7,8 the electrical properties of these low and high-k materials are reduced relative to SiO 2 , and there are significant electrical reliability concerns [9][10][11] as the industry seeks to continue to implement these materials in future ,15 nm and beyond technologies. 12,13 Specific electrical reliability concerns for low-and high-k dielectrics include line-line interconnect 14,15 and gate dielectric leakage, 16,17 dielectric breakdown (V bd ), [18][19][20] time-dependent dielectric breakdown, [21][22][23][24] stress-induced leakage currents, 25,26 bias temperature instabilities, 27,28 charge trapping, [29][30][31][32] and a host of other charge-related buildup phenomena. 33,34 Despite the wide range of reliability concerns, a key ingredient in the models for all of these phenomena is some type of "defect" or "trap" in the dielectric material.…”