Improvement of Amorphous InGaZnO Thin-Film Transistor With Ferroelectric ZrO_x/HfZrO Gate Insulator by 2 Step Sequential Ar/O₂ Treatment

Effect of Gate Bias Stress on the Electrical Characteristics of Ferroelectric Oxide Thin-Film Transistors with Poly(Vinylidenefluoride-Trifluoroethylene)

“…Recently, various attempts have been made to exploit OxTFTs as a ferroelectric or charge trap memory device [ 7 , 8 ]. Ferroelectric oxide thin-film transistors (FeOxTFTs), which use ferroelectrics as a gate insulator, facilitate programing and erasing operations at relatively low voltages compared to charge trap transistors [ 9 ].…”

Low Operating Voltage and Immediate Read‐After‐Write of HZO‐Based Si Ferroelectric Field‐Effect Transistors with High Endurance and Retention Characteristics

“…[ 28 ] However, there is a trade‐off in that the temperature of the post‐metallization annealing for inducing the ferroelectric orthorhombic phase is increased. Other approaches have been reported to improve device performance by surface treatment such as microwave annealing [ 29,30 ] and plasma treatment, [ 31,32 ] and to improve ferroelectricity by generating defects, [ 33,34 ], i.e., oxygen vacancy, using sputtering and ion bombardment. In particular, oxygen vacancy in HZO film plays an important role in favoring the formation of a ferroelectric orthorhombic phase during the annealing process.…”

Device modeling of oxide–semiconductor channel antiferroelectric FETs using half-loop hysteresis for memory operation

“…5,6) For such a 3D vertical structure, oxidesemiconductor (OS) channels such as IGZO, which was originally developed for flat-panel display applications, [7][8][9] have been recently proposed as a potential alternative to conventional poly-Si channels because of their high mobility and no low-k interfacial layer formation between Fe-HfO 2 and OS layers. [10][11][12][13][14][15][16][17][18][19] However, there is a challenge for 3D vertical FeFETs with OS channels: an OS is typically an ntype channel material that hardly generates minority hole carriers, resulting in a weak erase issue in OS channel FeFETs. 20) Previous works theoretically and experimentally demonstrated an improved memory window (MW) with a floating-body channel by using a shorter gate length (L g ) and thinner channel due to the enhanced electric field in the Fe layer.…”