Improvement of Stress Stability in Back Channel Etch-Type Amorphous In-Ga-Zn-O Thin Film Transistors with Post Process Annealing

Abstract

The electronic structures and electronic states near the back channel surfaces in amorphous In-Ga-Zn-O (a-IGZO) thin film transistors (TFTs) were investigated. The X-ray photoelectron spectroscopy (XPS) analysis revealed that, due to insufficient wet-etching of source/drain (S/D) of Mo metal, continuous sub-gap states formed throughout the bandgap, which induced degradation of the subthreshold swing of the TFTs with a back channel etch (BCE) structure. The stability under the negative bias thermal illumination stress (NBTIS) in the a-IGZO BCE-type TFTs was worse than that of conventional etch stop layer (ESL)-type TFTs. The Vth shift (ΔVth) increased from −2.5 V to −4.0 V with a hump-shaped variation. According to photoinduced transient spectroscopy (PITS) analysis, a broader shoulder of around 160 K clearly appeared in PITS spectra from the a-IGZO thin films with the BCE structure. The effect of post process annealing applied as the final process step of the TFT fabrication (post-annealing) was also examined against the a-IGZO BCE-TFTs. As the post-annealing temperature was increased, the peak at around 160 K which is associated with the hydrogen-related traps in a-IGZO thin film was markedly decreased. The results for the post-annealing at 300°C suggested a decrease in density of trap states which originated from depletion of Zn. A marked improvement of the stress stabilities under the positive bias, thermal stress (PBTS) was also observed as well as NBTIS.

Evaluation of stress stabilities in amorphous In–Ga–Zn–O thin-film transistors: Effect of passivation with Si-based resin

“…Note that sufficient S=D overetching is necessary to avoid SS degradation since Mo residues induce broad subgap states throughout the band gap. 14) Figures 3(a variations of the transfer curves obtained from the a-IGZO BCE-TFTs under the NBTIS test. TFT-4, which had the PV layer of stacked D-SiN x =Si resin=SiO x , exhibited μ sat , SS, and V th of 7.9 cm 2 V −1 s, 0.36 V=decade, and −1.0 V, respectively.…”

“…Furthermore, to evaluate the trap states in the channel region of the a-IGZO TFTs, the PITS measurements were performed using test devices equivalent to the actual TFT structures. [12][13][14] The test devices were fabricated with the same fabrication process and structure as those for the a-IGZO TFTs except for a lack of Mo that acts as a gate electrode. The distance between two electrodes was 5 mm.…”

“…It was found that postannealing, which is a type of annealing applied after the TFT fabrication is completed, was effective for improving the NBTIS stability. 14) With regard to the manufacturing process including the wet etching of the source=drain (S=D) metal, the formation of the passivation (PV) layer, and other post integration processes in BCE-TFTs, each process condition should be carefully selected to obtain good and stable TFT characteristics. In particular, to optimize the BCE process conditions based on the TFT characteristics, both the initial and resultant transfer characteristics after the stress test should be determined.…”

Impact of the Source/Drain Electrode Process on the Mobility-Threshold Trade-Off for InSnZnO Thin-Film Transistors

“…InSnZnO (ITZO) has great potential for use in transparent or flexible electronics application. , The orbitals of Sn 5s and In 5s in ITZO show large overlapping parts, the synergic intercalation between which widens the electron transmission channel and improves the intrinsic mobility compared with IGZO (InGaZnO). , Moreover, Sn-rich oxides have strong corrosion resistance to common acids and bases, which is promising for back-channel-etch (BCE) devices . Compared with the etch-stop-layer (ESL) ones, it can reduce at least one lithography process, simplify the process steps, and reduce the preparation cost . However, reported ITZO TFTs commonly adopted ITO S/D electrodes (rather than the metal Mo-based process frequently used in the IGZO-TFT production line) or a lift-off electrode process or ESL configuration. ,,, This implies that the S/D process has a big impact on the device performance of ITZO TFTs.…”

“…19 with the etch-stop-layer (ESL) ones, it can reduce at least one lithography process, simplify the process steps, and reduce the preparation cost. 20 However, reported ITZO TFTs commonly adopted ITO S/D electrodes (rather than the metal Mo-based process frequently used in the IGZO-TFT production line 21 ) or a lift-off electrode process or ESL configuration. 10,15,16,22 This implies that the S/D process has a big impact on the device performance of ITZO TFTs.…”