Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks

Ghosh, Anandaroop; Sauseng, Paul; Bhunia, Swarup

doi:10.1109/tvlsi.2013.2271696

Cited by 13 publications

(2 citation statements)

References 22 publications

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“…It is a general consensus that using FPGA as a computational resource can reduce the system energy consumption. Previous research [12,13] has reported the FPGA energy efficiency considering one or more specific tasks under predefined situations. However, this could be incorrect especially for periodic tasks.…”

Section: Motivations and Problem Formulationmentioning

confidence: 99%

Dynamic Energy Management of FPGA Accelerators in Embedded Systems

Hosseinabady

Nunez-Yanez

2018

ACM Trans. Embed. Comput. Syst.

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In this paper, we investigate how to utilise an FPGA in an embedded system to save energy. For this purpose, we study the energy efficiency of a hybrid FPGA-CPU device that can switch task execution between hardware and software with focus on periodic tasks. To increase the applicability of this task switching, we also consider the voltage and frequency scaling (VFS) applied to the FPGA to reduce the system energy consumption. We show that in some cases, if the task's period is higher than a specific level, the FPGA accelerator cannot reduce the energy consumption associated to the task and the software version is the most energy efficient option. We have applied the proposed techniques to a robot map creation algorithm as a case study which shows up to 38% energy reduction compared to the FPGA implementation. Overall, experimental results show up to 48% energy reduction by applying the proposed techniques at runtime on thirteen individual tasks.

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Section: Motivations and Problem Formulationmentioning

confidence: 99%

Dynamic Energy Management of FPGA Accelerators in Embedded Systems

Hosseinabady

Nunez-Yanez

2018

ACM Trans. Embed. Comput. Syst.

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“…Finally, at the level of architecture, many FPGA design methods, such as increasing the size of the look up tables LUTs in the configurable logic blocks CLBs from 4-input to 6-input, so each LUT is used for more logic and fewer interconnects is required [5]. Unfortunately, all these techniques at various levels can potentially degrade the performance of some compute-intensive applications, and cannot reduce sufficiently the energy consumption for many of them [6].…”

Section: Introductionmentioning

confidence: 99%

Energy-efficient imprecise reconfigurable computing through probabilistic domain transformation

Alawad

Lin

2014

2014 IEEE Dallas Circuits and Systems Conference (DCAS)

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Many DSP applications naturally possess so-called "inherent error resilience", meaning certain degrees of computational errors would not noticeably impair their eventual quality of results. Such a phenomenon offers an interesting opportunity to significantly improve the overall energy efficiency of these DSP applications at the cost of minute degradations in computing accuracy. This work presents a probabilistic-based methodology to perform high-performance DSP applications while achieving low power consumption. Deviating from all published approximate computing methods, our solution leverages a fundamental probability principle to implement a reconfigurable finite impulse response FIR digital filter specifically designed for FPGA-based image and video processors. Our method is trading off performance efficiency and power consumption against accuracy of the output results.To validate this proposed probabilistic architecture for discrete FIR filter, We have developed a 16-tap FIR filter with Virtex 5 FPGA devices (XC5VSX95T-1FF1136). Our prototype of probabilistic-based reconfigurable FIR filter consumes 9 times less power than multiplier-based FIR filter and dissipates 43.13 µJ in dynamic energy consumption to perform filtering on a (256×256) pixel image. We believe that this new architecture can be exploited in all the real-time applications in which energyefficient FIR filters are required and it can be realized with many other FPGA device families.

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