Improving ESD Protection Robustness Using SiGe Source/Drain Regions in Tunnel FET

Abstract

Currently, a tunnel field-effect transistor (TFET) is being considered as a suitable electrostatic discharge (ESD) protection device in advanced technology. In addition, silicon-germanium (SiGe) engineering is shown to improve the performance of TFET-based ESD protection devices. In this paper, a new TFET with SiGe source/drain (S/D) regions is proposed, and its ESD characteristics are evaluated using technology computer aided design (TCAD) simulations. Under a transmission line pulsing (TLP) stressing condition, the triggering voltage of the SiGe S/D TFET is reduced by 35% and the failure current is increased by 17% in comparison with the conventional Si S/D TFET. Physical insights relevant to the ESD enhancement of the SiGe S/D TFET are provided and discussed.

Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

“…Figure 2a,b are schematic diagrams of SiGe S/D PNN TFET and Conventional TFET, both of which have SiGe Source/Drain. In order to facilitate heat dissipation, the device size is not set to a very small value [27,28]. The high K material of the gate medium is HfO2.…”

Optimization of Tunnel Field-Effect Transistor-Based ESD Protection Network

“…The quasi-statistic characteristics are obtained by averaging the transient data in an interval of 60 to 90 ns. According to [18,19], the lattice temperature is usually used as the criterion to determine device failure in simulations. The critical failure temperature is usually defined as a value that is hundreds of degrees kelvin lower than the melting temperature.…”

“…In the simulation, the current pulse has a rise time of 10 ns and a pulse width of 100 ns to mimic the human body model ESD event [12,14] The quasi-statistic characteristics are obtained by averaging the transient data in an interval of 60 to 90 ns. According to [18,19], the lattice temperature is usually used as the criterion to determine device failure in simulations. The critical failure temperature is usually defined as a value that is hundreds of degrees kelvin lower than the melting temperature The critical failure temperatures of the full-silicon TFET and Ge-source TFET in the simulation are set to 1200 and 890 K, respectively.…”

Characteristics of Tunnel Field-effect Transistors under Power-on Electrostatic Discharge and Electrical Overstress Conditions

“…(5)(6)(7) One of the advantages of TEFTs is that they are compatible with CMOS technology; thus, the concept of mixed MOSFET-TFET circuits was proposed and some new applications such as electrostatic discharge (ESD) protection with a TFET have been investigated. (8)(9)(10)(11)(12)(13)(14) It was found that a TFET can be a better choice than a shallow trench isolation (STI) diode in a whole-chip ESD protection network. (10) Recently, an increasing number of IC failures have been observed under power-on ESD and electrical overstress (EOS) conditions.…”