Improving Linear Test Data Compression

Abstract

Abstract-The output space of a linear decompressor must be sufficiently large to contain all the test cubes in the test set. The ideas proposed in this paper transform the output space of a linear decompressor so as to reduce the number of inputs required thereby increasing compression while still keeping all the test cubes in the output space. Scan inversion is used to invert a subset of the scan cells while reconfiguration modifies the linear decompressor. Any existing method for designing a linear decompressor (either combinational or sequential) can be used first to obtain the best linear decompressor that it can. Using that linear decompressor as a starting point, the proposed methods improve the compression further. The key property of scan inversion is that it is a linear transformation of the output space and, thus, the output space remains a linear subspace spanned by a Boolean matrix. Using this property, a systematic procedure based on linear algebra is described for selecting the set of inverting scan cells to maximize compression. A symbolic Gaussian elimination method to solve a constrained Boolean matrix is proposed and utilized for reconfiguring the linear decompressor. The proposed schemes can be utilized in various design flow scenarios and require no or very little hardware overhead. Experiments indicate that significant improvements in compression can be achieved.Index Terms-Linear decompression, linear feedback shift register (LFSR) reseeding, on-chip decompression, test data compression, XOR network.

High-Quality Statistical Test Compression With Narrow ATE Interface

“…In [19], ring generators were proposed as an alternative to classical LFSRs and in [20], embedded deterministic test was presented. Other well known techniques have been presented in [21]- [28]. However, linear-based methods do not exploit the high correlation between test cubes' specified bits.…”

Test compression for circuits with multiple scan chains

“…The idea of test compression is based on the fact that the modern circuits can be typically tested with the deterministic test patterns containing more than 95% of don't care bits. The test pattern care bits are obtained on the decompressor outputs by unrolling the decompressor seeds while don't care test bits are replaced by pseudorandom values that are obtained on the resting decompressor outputs positions [12], [1], [17], [13] and [22]. Special finite automata usually accompanied with a phase shifter that can reach demanded specific logical values on appropriate outputs in appropriate clock cycles and generate pseudorandom values on the rest of outputs can be used for the test pattern decompression.…”

“…This feature is crucial for the speed of test pattern encoding. LFSRs and-or ring generators with additional phase shifters are widely used for decompression of test patterns [8], [12], [1], [17], [9], [14], [22], [2], [7] and [11]. Encoding of a test pattern using a linear automaton requires solving the corresponding system of linear equations, one equation for one specified bit.…”

Low Power Test-Compression for High Test-Quality and Low Test-Data Volume

“…Even though traditional test data compression techniques (like for example [2], [4], [12], [13], [14], [15], [19]) are very efficient in compressing test data, they elevate switching activity beyond acceptable levels. Increased power dissipation often causes good chips to fail testing, degrading thus production yield.…”

“…However, these techniques suffer from low compression efficiency and additionally they are not suitable for modern cores consisting of large number of scan chains. Linear decompressors on the other hand achieve very high compression but they are not power-friendly as they fill the unspecified ('x') values in a random way [2], [4], [14], [15], [19]. Recently, linear decompressors emerged, that target low switching activity during scan testing [10], [11], [16], [17].…”