Improving PCM Endurance with a Constant-Cost Wear Leveling Design

Chang, Yang-Lang; Hsiu, Pi-Cheng; Chang, Yuan-Hao; Chen, Chi-Hao; Kuo, Tei-Wei; Wang, Cheng-Yuan Michael

doi:10.1145/2905364

Cited by 22 publications

(5 citation statements)

References 33 publications

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“…The IPC consumed by each benchmark is calculated based on the mathematical Equation ( 2) and is presented in Table 2. The proposed IPC_DPC model is compared with 3 distinct existing models FNW [5], FPC [4], BDI [6], and DFPC [17] based on the parameters. The experimental setup used for the evaluation of the proposed module is tabulated in Table 1.…”

Section: Resultsmentioning

confidence: 99%

“…Many works are proposed to improve the endurance of NVRAM. Most of the proposed endurance improvement methods involve constantly monitoring the wear levels of all lines of memory or employing a coarse-grained wear-leveling based on a global counter, resulting in a device's enhancement being limited by the weakest endurance cell or erroneous wear-leveling [4][5][6][7][8][9][10][11]. The mentioned criticalities are addressed in the proposed framework in this paper.…”

Section: Introductionmentioning

confidence: 99%

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Energy efficient IPC based dual compression for endurance enhancement of NVRAM as main memory in embedded devices

Palanivelu

Radhakrishnan

Kumar³

et al. 2023

IET Communications

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The Non‐Volatile Random Access Memory (NVRAM) is recently identified as the most upcoming main memory technology in Embedded and Internet of Things (IoT) systems due to its appealing qualities like zero static power consumption and great memory cell density. On the other hand, most NVRAMs have low write endurance due to workload‐induced write variance, leading to more write activity at a few blocks of memory than the other blocks. Improving the endurance of NVRAM on embedded architectures is very critical due to the limited constraints of Embedded architectures. The main goal of this paper is to address the complexity of NVRAM designs, with a focus on embedded boards, and to create a prototype that enhances NVRAM endurance using a compression technique. Furthermore, this framework is not particular to a single NVRAM device. An Instruction Per Cycle based Dynamic Pattern Compression (IPC_DPC) model is developed to address NVRAM's high write latency and low endurance. The primary goal of the proposed IPC_DPC model is to minimize the energy utilization and latency of heavy workloads during the execution by pre‐determining the workload's instruction cycles. The IPC_DPC model initially divides the Low IPC and High IPC workloads and then compresses the workloads dynamically based on their IPC values compared to the threshold factor. As a result, IPC_DPC improves the compression ratio and reduces the write latencies associated with traditional compressors, significantly reducing the write activity and improving the lifetime of NVRAM. We implemented the proposed IPC_DPC model using GEM5 with a Raspberry Pi board and took IoMT, MiBench, and EEMBC benchmarks for evaluation. Compared to FPC, BDI, FNW, and DFPC models, the proposed IPC_DPC model is shown to be more efficient in terms of compression ratio (56.05%) and energy reduction (17%).

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Energy efficient IPC based dual compression for endurance enhancement of NVRAM as main memory in embedded devices

Palanivelu

Radhakrishnan

Kumar³

et al. 2023

IET Communications

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“…To do so, we adopt the lifetime model in [51], which estimates the lifetime of a memory module driven by the access patterns observed in our Chrome workload. We assume a conservative Optane cell endurance of 10 6 writes [231] (i.e., the same cell endurance of PCM-based memory cells [67], [232], [233]) and an optimistic wearleveling mechanism that evenly distributes write requests across all cells of the Intel Optane media (which the Intel Optane SSD is reported to implement [234]). Our model shows that the lifetime of the Optane configuration without (with) Zswap enabled when executing our Chrome workload is 4.5 (8.3) years.…”

Section: B Reducing Tail Latency By Enabling a Compressed Ram Cachementioning

confidence: 99%

“…Many prior works [51], [56], [60], [79], [228], [229], [232], [233], [235], [251], [252], [253], [254], [255], [256], [257], [258], [259] aim to reduce the impact of emerging NVMs on overall system energy consumption and lifetime. The great majority of such works aim to (i) reduce the number of write operations the system issue to the NVM device using techniques such as caching [51], [79], writeaware data mapping and data allocation algorithms [60], [79], [229], and data compression [228]; and (ii) distribute write operations across NVM cells using diverse wear-leveling techniques [56], [232], [233], [235], [251], [253], [254], [255], [256], [257], [259]. We believe such approaches can be employed to mitigate the limitations of NVMs in consumer devices.…”

Section: A Overall Limitations Of the Technologymentioning

confidence: 99%

Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSD

Oliveira,

Ghose,

Gómez-Luna

et al. 2023

IEEE Access

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DRAM scalability is becoming a limiting factor to the available memory capacity in consumer devices. As a potential solution, manufacturers have introduced emerging non-volatile memories (NVMs) into the market, which can be used to increase the memory capacity of consumer devices by augmenting or replacing DRAM. In this work, we provide the first analysis of the impact of extending the main memory space of consumer devices using off-the-shelf NVMs. We equip real web-based Chromebook computers with the Intel Optane solid-state drive (SSD), which contains state-of-the-art low-latency NVM, and use the NVM as swap space. We analyze the performance and energy consumption of the Optane-equipped Chromebooks, and compare this with (i) a baseline system with double the amount of DRAM than the system with the NVM-based swap space; and (ii) a system where the Intel Optane SSD is naively replaced with a state-of-theart NAND-flash-based SSD. Our experimental analysis reveals that while Optane-based swap space provides a cost-effective way to alleviate the DRAM capacity bottleneck in consumer devices, naive integration of the Optane SSD leads to several system-level overheads, mostly related to (1) the Linux block I/O layer, which can negatively impact overall performance; and (2) the off-chip traffic to the swap space, which can negatively impact energy consumption. To reduce the Linux block I/O layer overheads, we tailor several system-level mechanisms (i.e., the I/O scheduler and the I/O request completion mechanism) to the currentlyrunning application's access pattern. To reduce the off-chip traffic overhead, we leverage an operating system feature (called Zswap) that allocates some DRAM space to be used as a compressed in-DRAM cache for data swapped between DRAM and the Intel Optane SSD, significantly reducing energy consumption caused by the off-chip traffic to the swap space. We conclude that emerging NVMs are a cost-effective solution to alleviate the DRAM capacity bottleneck in consumer devices, which can be further enhanced by tailoring system-level mechanisms to better leverage the characteristics of our workloads and the NVM.

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“…Wear-Leveling Techniques for PCM. There are many prior works that propose wear-leveling techniques to enhance PCM lifetime [2,[21][22][23]25,29,34,41,61,62,77,82,83,88,95,116,117,[120][121][122]. These works propose di erent techniques to optimize wear-leveling via swapping and remapping data.…”

Section: Wear-leveling Techniquesmentioning

confidence: 99%

WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders

Yavits¹,

Orosa²,

Mahar³

et al. 2020

Preprint

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Resistive memories have limited lifetime caused by limited write endurance and highly non-uniform write access patterns. Two main techniques to mitigate endurance-related memory failures are 1) wear-leveling, to evenly distribute the writes across the entire memory, and 2) fault tolerance, to correct memory cell failures. However, one of the main open challenges in extending the lifetime of existing resistive memories is to make both techniques work together seamlessly and e ciently.To address this challenge, we propose WoLFRaM, a new mechanism that combines both wear-leveling and fault tolerance techniques at low cost by using a programmable resistive address decoder (PRAD). The key idea of WoLFRaM is to use PRAD for implementing 1) a new e cient wear-leveling mechanism that remaps write accesses to random physical locations on the y, and 2) a new e cient fault tolerance mechanism that recovers from faults by remapping failed memory blocks to available physical locations. Our evaluations show that, for a Phase Change Memory (PCM) based system with cell endurance of 10 8 writes, WoLFRaM increases the memory lifetime by 68% compared to a baseline that implements the best state-of-the-art wear-leveling and fault correction mechanisms. WoLFRaM's average / worst-case performance and energy overheads are 0.51% / 3.8% and 0.47% / 2.1% respectively.

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Improving PCM Endurance with a Constant-Cost Wear Leveling Design

Cited by 22 publications

References 33 publications

Energy efficient IPC based dual compression for endurance enhancement of NVRAM as main memory in embedded devices

Energy efficient IPC based dual compression for endurance enhancement of NVRAM as main memory in embedded devices

Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSD

WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders

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