Improving Performance Guarantees in Wormhole Mesh NoC Designs

2017 Euromicro Conference on Digital System Design (DSD)

et al. 2017

Self Cite

Abstract-Wormhole-based NoCs (wNoCs) are widely accepted in high-performance domains as the most appropriate solution to interconnect an increasing number of cores in the chip. However, wNoCs suitability in the context of critical real-time applications has not been demonstrated yet. In this paper, in the context of probabilistic timing analysis (PTA), we propose a PTA-compatible wNoC design that provides tight time-composable contention bounds. The proposed wNoC design builds on PTA ability to reason in probabilistic terms about hardware events impacting execution time (e.g. wNoC contention), discarding those sequences of events occurring with a negligible low probability. This allows our wNoC design to deliver improved guaranteed performance. Our results show that WCET estimates of applications running on top of probabilistic wNoCs are reduced by 40% and 75% on average for 4x4 and 6x6 wNoC setups respectively when compared against deterministic wNoCs.

Section: B Reducing Contention In Probabilistic Wnocsmentioning

confidence: 56%

Section: Introductionmentioning

confidence: 99%

Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis

Slijepcevic

Hernández

2017 Euromicro Conference on Digital System Design (DSD)

et al. 2017

Self Cite

“…We refer to the k-th packet generated by flow F i as r k i . In general, one-flit packets are usually preferred for real-time workloads in order to improve wNoCs performance guarantees [29].…”

Section: Network Baselinementioning

confidence: 99%

“…In the context ot timing correctness, the main focus of this paper, wNoCs complicate the derivation of good-quality performance guarantees since, unlike buses or other existing centralized network architectures, wNoCs perform the arbitration of communication flows in a distributed manner. In this line, some works show that, while reliable contention upper bounds can be provided for Commercial off-the-shelf (COTS) wNoCs [33] [30] [29], those bounds are pessimistic, preventing an efficient use of high-performance wNoCs for mixedcriticality real-time embedded systems (RTES).…”

mentioning

confidence: 99%

Time-Randomized Wormhole NoCs for Critical Applications

Slijepcevic

Hernández

J. Emerg. Technol. Comput. Syst.

et al. 2019

Self Cite

Wormhole-based NoCs (wNoCs) are widely accepted in high-performance domains as the most appropriate solution to interconnect an increasing number of cores in the chip. However, wNoCs suitability in the context of critical real-time applications has not been demonstrated yet. In this paper, in the context of probabilistic timing analysis (PTA), we propose a PTA-compatible wNoC design that provides tight timecomposable contention bounds. The proposed wNoC design builds on PTA ability to reason in probabilistic terms about hardware events impacting execution time (e.g. wNoC contention), discarding those sequences of events occurring with a negligible low probability. This allows our wNoC design to deliver improved guaranteed performance w.r.t. conventional time-deterministic setups. Our results show that performance guarantees of applications running on top of probabilistic wNoC designs improve by 40% and 93% on average for 4x4 and 6x6 wNoC setups, respectively.

“…Static XY-routing for NoCs and round-robin or random arbitrations combined with smart virtual channel allocation are good instances of that notion, as they ease capturing worst-case scenarios while also assuring a worst-case behavior not too far apart from the average one. Conversely, adaptive routing and dynamic virtual channel allocation solutions increase that gap, often earning only marginal improvement to the average case [10].…”

Section: Common Principlesmentioning

confidence: 99%

Reconciling Time Predictability and Performance in Future Computing Systems

Cazorla¹,

Mezzetti

et al. 2018

IEEE Des. Test

Self Cite

Abstract-The demand for guaranteed, hence predictable, performance in the real-time systems domain is projected to increase by several orders of magnitude in the next few years, while its weight in the mainstream market is on the rise. Satisfying this need in a cost-effective manner compels system architects to use high-performance hardware units, which however have disruptive effects on current timing verification practice. This paper presents low-overhead solutions for hardware design and timing analysis to help attain the desired level of predictable performance in all application domains with assurance needs, also contributing to the universal pursuit of performance guarantees.