Improving the methodology to build non-series-parallel transistor arrangements

Exploring Independent Gates in FinFET-Based Transistor Network Generation

“…The first step (A), tries to find efficient arrangements through a graph-based structure called SP kernel, which was proposed in [12]. The second step (B), presents a strategy to perform simple factoring operations considering some constraints to maximize the merge of series and parallel transistors.…”

“…It happens because some redundant literals, in a factored expression or in a graph-based solution, can contribute to find the best series and parallel merging and to decrease the total number of FinFETs in a network. Therefore, as both the conventional factorization methods and the graph-based techniques aim to minimize the literal count, these methods [11][12][13] may not be the best alternative to generate IG FinFET transistor networks.…”

“…Example 3: When the goal is to minimize the transistor count, the non-series-parallel (NSP) arrangements are a feasible way to do that [12]. In general, the graph-based techniques are able to find NSP arrangements while the factorization methods are limited to series-parallel (SP) arrangements.…”

“…Request permissions from Permissions@acm.org. There are many different methods available in the literature to decrease transistor count and to generate optimized networks to implement logic gates [11][12][13]. Such methods are able to deliver satisfactory solutions for single gate devices, i. e. conventional CMOS or SG FinFET.…”

“…Such methods are able to deliver satisfactory solutions for single gate devices, i. e. conventional CMOS or SG FinFET. In general, these methods aim to minimize the maximum number of literals in a Boolean expression by applying factorization [11] or graph-based optimizations [12][13]. Traditionally, minimize the number of literals leads to a reduced transistor network.…”