Transistor network optimization represents an effective way of improving VLSI circuits. This paper proposes a novel method to automatically generate networks with minimal transistor count, starting from an irredundant sum-of-products expression as the input. The method is able to deliver both series-parallel (SP) and non-SP switch arrangements, improving speed, power dissipation, and area of CMOS gates. Experimental results demonstrate expected gains in comparison with related approaches.

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This paper proposes the utilization of factored forms in logic synthesis for memristive material implication stateful logic. Factored forms have not been explored by previous works due to expected increasing on device count. We present an algorithm to obtain factored forms computable with minimum number of memristors. Comparison to previous works shows an average reduction of 12% in the number of operations to compute 4-input Boolean functions.

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