Graph-Based Transistor Network Generation Method for Supergate Design

Abstract

Transistor network optimization represents an effective way of improving VLSI circuits. This paper proposes a novel method to automatically generate networks with minimal transistor count, starting from an irredundant sum-of-products expression as the input. The method is able to deliver both series-parallel (SP) and non-SP switch arrangements, improving speed, power dissipation, and area of CMOS gates. Experimental results demonstrate expected gains in comparison with related approaches.

Topological characteristics of logic networks generated by a graph-based methodology

“…The set of functions are composed by the NSP handmade cells [11] (53 functions), the Nimomya's catalog [12] (402), the 4-input P-class [13] (3982), the NPN-class up to 5-input (NPN5) catalog (616125 functions) and the eleven variables and ninety-nine literals expression discussed as study case in [1] (named from here as 11-input) (1 function), which give us a total of 620563 Boolean functions.…”

“…Recently, graph-based approaches have demonstrated that they can be an efficient way to build optimized logic arrangements. Kernel Finder (KF) [1] is the state-of-art tool for the optimized transistor network generation. It is a graph-based methodology that can creates NSP networks via the path sharing technique.…”

“…As discussed before, considering the number of switches in its logic networks, graph-based methodologies already proved themselves as a valuable alternative to the efficient logic design [1,2]. However, those methodologies produce arrangements with some particular aspects, which affects the layout and some of the automatic layout generation tools (its placement methods, specially).…”

“…Considering the number of transistors in a logic network that are needed to implement a Boolean function, graph-based minimization methodologies have gained relevance recently [1,2]. Through the path sharing technique, these methods could reach several optimizations in the transistors count when compared to other methodologies [3,4].…”

“…This paper presents a flow to identify these topological characteristics on logic networks produced by a graph-based methodology. Starting from a Boolean function, we generate the optimized network in terms of number of transistors via the state-of-art tool Kernel Finder [1]. This procedure is followed by the next topologic tests: the planarity and duality check, the plans sizes check (which consists in the verification of the difference between the number of transistors that each logic plan contains) and the diffusion gap check.…”