Improving the Test of NoC-Based SoCs with Help of Compression Schemes

Dalmasso, Julien; Cota, Érika; Flottes, Marie-Lise; Rouzeyre, Bruno

doi:10.1109/isvlsi.2008.86

Cited by 18 publications

(5 citation statements)

References 19 publications

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“…The compression of test input data for reducing the number of test input pins was studied in [23]. Test-output compression to reduce output pin-count was discussed in [17].…”

Section: Related Prior Workmentioning

confidence: 99%

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Test-Delivery Optimization in Manycore SOCs

Agrawal

Richter

Chakrabarty

2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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We present two test-data delivery optimization algorithms for system-on-chip (SoC) designs with hundreds of cores, where a network-on-chip (NoC) is used as the interconnection fabric. We first present an effective algorithm based on a subsetsum formulation to solve the test-delivery problem in NOCs with arbitrary topology that use dedicated routing. We further propose an algorithm for the important class of NOCs with grid topology and XY routing. The proposed algorithm is the first to cooptimize the number of access points, access-point locations, pin distribution to access points, and assignment of cores to access points for optimal test resource utilization of such NOCs. Test-time minimization is modeled as an NoC partitioning problem and solved with dynamic programming in polynomial time. Both the proposed methods yield high-quality results and are scalable to large SOCs with many cores. We present results on synthetic grid topology NoC-based SOCs constructed using cores from the ITC'02 benchmark, and demonstrate the scalability of our approach for two SOCs of the future, one with nearly 1000 cores and the other with 1600 cores. Test scheduling under power constraints is also incorporated in the optimization framework.

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“…The compression of test input data for reducing the number of test input pins was studied in [23]. Test-output compression to reduce output pin-count was discussed in [17].…”

Section: Related Prior Workmentioning

confidence: 99%

“…Test-output compression to reduce output pin-count was discussed in [17]. Our approach can be extended to incorporate input and output compression as proposed in [23] and [17].…”

Section: Related Prior Workmentioning

confidence: 99%

Test-Delivery Optimization in Manycore SOCs

Agrawal

Richter

Chakrabarty

2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Several techniques have been published to achieve test vector compression. The scheme presented in this paper is based on the horizontal test data compression method [14], [15], [16].…”

Section: >= ℎ *mentioning

confidence: 99%

“…There are two natural ways of reducing the amount of test data to be stored: Vertical compression schemes [17], reduce the number of patterns to be stored and intend to minimize the amount of test data per ATE channel, whereas horizontal compression schemes [14], [15], [16], reduce the number of bits to be stored for each test pattern and address the reduction of the number of ATE channels, as described in the previous section. To achieve a vertical compression the test data are usually encoded as seeds of a standard pattern generator or of an arbitrary finite state machine.…”

Section: Literature Surveymentioning

confidence: 99%

Binary Difference Based Test Data Compression for NoC Based SoCs

Chaki

Giri

Rahaman

2012

2012 IEEE Computer Society Annual Symposium on VLSI

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The scaling of microchip technologies has enabled large scale and very complex systems-on-chip (SoC). The highperformance, flexible, scalable, simple to design and power efficient interconnection network, called the Network-on-chip (NoC), permits the system components to communicate effectively. This communication structure needs to be tested for correctness, which requires handling huge volume of test data. Thus, test data compression has now become essential to reduce test costs. It reduces test data volume which in turn decreases testing time. This work presents a new test data compression method based on binary difference and the corresponding decompression architecture. The major advantages of this compression technique include very high compression ratio, and a low-cost on-chip decoder. The effectiveness of the proposed approach is demonstrated by applying it to the full scan test data set of ISCAS'89 benchmark circuits.

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“…Here, existing approaches focus on scan-based testing of cores and deal with the design of appropriate wrappers, optimal wrapper configuration, as well as with test scheduling [3,4,18,26,27,29]. Recently, a first approach has been presented to improve core testing in NoCs through test data compression [13]. The authors propose a compression scheme based on the arithmetic difference of succeeding test patterns and attach an extra decompressor to each test input port.…”

Section: Introductionmentioning

confidence: 99%

Reusing NoC-infrastructure for test data compression

Froese

Ibers

Hellebrand

2010

2010 28th VLSI Test Symposium (VTS)

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Previous work on testing NoC-based systems has shown that the integrated network can be efficiently reused as test access mechanism (TAM). These approaches exploit the given infrastructure for data transportation. Beyond that, NoC-architectures for nanoscale systems also have to ensure a reliable communication by additional hardware and/or software measures. For example a cyclic redundancy check (CRC) may be added to protect the end-to-end communication between network resources. This paper presents an approach to reuse the CRC hardware for a compression scheme similar to LFSR-reseeding. The experimental results show that competitive compression ratios can be achieved at low extra cost. This way, core testing in NoC-based systems can benefit from test data compression even for standard cores without integrated decompressors.

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Improving the Test of NoC-Based SoCs with Help of Compression Schemes

Abstract: Re-using the network in a NoC-based

Cited by 18 publications

References 19 publications

Test-Delivery Optimization in Manycore SOCs

Test-Delivery Optimization in Manycore SOCs

Binary Difference Based Test Data Compression for NoC Based SoCs

Reusing NoC-infrastructure for test data compression

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