In-chip overlay metrology in 90 nm production

Abstract

We have inserted, measured and demonstrated good metrology performance on in-die overlay targets on product wafers. It is shown that scanner aberration induced pattern placement errors (PPE) can be measured, simulated and validated by CD-SEM, but the magnitude of the effect on late generation scanners is small -of the order of ~1.5 nm peak to peak across the slit. It is observed that in-die overlay data contains additional sources of variation beyond PPE and the results have been verified by SEM. It is demonstrated that current practices based on linear models do not capture in-die variations which significantly impacts model residuals.Currently, in-die target insertion is an insurance policy which enables in-die trouble shooting when process issues are suspected and will potentially improve lot dispositioning in the future.

45-nm design rule in-die overlay metrology on immersion lithography processes

“…non-segmented AIM targets with pitch size 2.1 µm were evaluated compared with two standard size targets:(1) conventional Bar-in-Bar (BiB) target with outer target size 22 µm and (2) 20 µm non-segmented AIM target 2 with pitch size 2.4 µm. Target images can be found in Overlay metrology target designs, evaluated in this publication.…”