In-line testing of blind TSVs for 3D IC integration and M/NEMS packaging

Xu, Yongde; Wang, Guanjiang; Sun, Xiankai; Fang, Runiu; Miao, Min; Jin, Yufeng

doi:10.1109/nems.2013.6559722

Cited by 3 publications

(1 citation statement)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…No active device is made on the TSV adapter board. The measurement of TSV-related leakage current is concerned with the leakage current between two adjacent TSVs through the side wall insulation layer and the substrate [10][11]. Before the substrate thinning, the leakage current of two blind hole TSV pairs is measured by the probe station, and the loading voltage is from 0 to 50V.…”

Section: Tsv Leakage Current Testmentioning

confidence: 99%

Study on TSV insulating medium based on SACVD process

Shen,

Wang,

et al. 2024

J. Phys.: Conf. Ser.

View full text Add to dashboard Cite

TSV silicon switching board technology has the advantages of short global interconnection, small delay, low power consumption and high integration. The dielectric insulation performance in the TSV hole will directly affect the signal integrity and power integrity of the TSV silicon switching board. The insulating dielectric layer of TSV requires good forming ability and step covering, and lower leakage current and good heat resistance reliability. In this paper, the filling capacity of SACVD process is analyzed, the coverage rate of SACVD process is studied under different process parameters, and the leakage current of silicon dioxide film is measured by planar capacitance structure. Finally, the leakage current test of the TSV pairs is carried out online. Before the substrate thinning, the leakage current of the two blind hole TSV pairs is measured by the probe station. The voltage ranges form 0 to 50V, and the leakage current ranges from a few pA to a few hundred pA.

show abstract

Section: Tsv Leakage Current Testmentioning

confidence: 99%

Study on TSV insulating medium based on SACVD process

Shen,

Wang,

et al. 2024

J. Phys.: Conf. Ser.

View full text Add to dashboard Cite

show abstract

Low-frequency testing of through silicon vias for defect diagnosis in three-dimensional integration circuit stacking technology

Miao

Fang

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

Study of TSV leakage current and breakdown voltage

Wang

Sun

et al. 2013

2013 14th International Conference on Electronic Packaging Technology

View full text Add to dashboard Cite

Three potential contributing factors to the TSV leakage and breakdown are discussed and analyzed in this study. In addition, an in-line testing methodology is put forward so that leakage and breakdown data could be easily obtained. Finite element method simulation was used to illustrate the testing principle, and experimental test were carried out for validation. It was found that the most contributing factor to the TSV leakage and breakdown is the uniformity of the insulator layer thickness, while via-diameter and pitch between TSVs are factors of failure mechanism of the low-frequency characteristics.

show abstract

In-line testing of blind TSVs for 3D IC integration and M/NEMS packaging

Cited by 3 publications

References 4 publications

Study on TSV insulating medium based on SACVD process

Study on TSV insulating medium based on SACVD process

Low-frequency testing of through silicon vias for defect diagnosis in three-dimensional integration circuit stacking technology

Study of TSV leakage current and breakdown voltage

Contact Info

Product

Resources

About