In-Plane Monolithic Integration of Scaled III-V Photonic Devices

Abstract

It is a long-standing goal to leverage silicon photonics through the combination of a low-cost advanced silicon platform with III-V-based active gain material. The monolithic integration of the III-V material is ultimately desirable for scalable integrated circuits but inherently challenging due to the large lattice and thermal mismatch with Si. Here, we briefly review different approaches to monolithic III-V integration while focusing on discussing the results achieved using an integration technique called template-assisted selective epitaxy (TASE), which provides some unique opportunities compared to existing state-of-the-art approaches. This method relies on the selective replacement of a prepatterned silicon structure with III-V material and thereby achieves the self-aligned in-plane monolithic integration of III-Vs on silicon. In our group, we have realized several embodiments of TASE for different applications; here, we will focus specifically on in-plane integrated photonic structures due to the ease with which these can be coupled to SOI waveguides and the inherent in-plane doping orientation, which is beneficial to waveguide-coupled architectures. In particular, we will discuss light emitters based on hybrid III-V/Si photonic crystal structures and high-speed InGaAs detectors, both covering the entire telecom wavelength spectral range. This opens a new path towards the realization of fully integrated, densely packed, and scalable photonic integrated circuits.

Single-mode emission from a monolithically integrated III-V/Si topological lattice

“…Below threshold, we observe a blue shift of the emission wavelength that we attribute to free carrier plasma dispersion effects. This is something typically observed for similarly sized devices 25,37,38 . At the same time, the FWHM of the emission peak narrows significantly with its lowest value of 3 nm at threshold, where it becomes limited by the peak jitter during each individual pulse.…”

Single-Mode Emission in InP Microdisks on Si Using Au Antenna

“…Small mode volumes and low thresholds can be achieved by various cavity types, like photonic crystal cavities, − metal-clad cavities, − semiconductor-on-metal cavities, , or whispering gallery mode (WGM) microdisk cavities, − based on total internal reflection. The latter have the advantage of possessing a simple fabrication scheme.…”

GaAs Templates Selectively Grown on Silicon-on-Insulator for Lasers in Silicon Photonics

“…Template-assisted selective epitaxy (TASE) and lateral aspect ratio trapping (LART) are the alternative growth techniques in selective epitaxy to enable fabrication of photonic devices in lateral configuration. 23,24 These two techniques offer an ideal solution for the monolithic III−V/ Si platform with potential efficient light coupling in device designs. While GaAs microdisk lasers (MDLs) emitting at 860 nm have been demonstrated on (001) Si by TASE, 25 the device with dimensions in the deep subwavelength scale limit the device design and future applications.…”

“…Optically pumped nanoridge lasers and III–V photodetectors have been demonstrated on silicon-on-insulator (SOI) wafers using selective heteroepitaxy techniques such as vertical ART and nanoridge engineering. − However, the small material volume in the high aspect ratio nanometer-scale space makes demonstration of electrically driven devices challenging, and the coupling efficiency is likely to be degraded by the height difference between the III–V active region and Si waveguides. Template-assisted selective epitaxy (TASE) and lateral aspect ratio trapping (LART) are the alternative growth techniques in selective epitaxy to enable fabrication of photonic devices in lateral configuration. , These two techniques offer an ideal solution for the monolithic III–V/Si platform with potential efficient light coupling in device designs. While GaAs microdisk lasers (MDLs) emitting at 860 nm have been demonstrated on (001) Si by TASE, the device with dimensions in the deep subwavelength scale limit the device design and future applications .…”