2017
DOI: 10.1109/led.2017.2649599
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In Situ <italic>O</italic>xide, <italic>G</italic>aN Interlayer-Based Vertical Trench MOS<italic>FET</italic> (<italic>OG-FET</italic>) on Bulk GaN substrates

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Cited by 139 publications
(50 citation statements)
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“…The gate recess utilized a sequential dry and wet etching in order to result in smooth and ≈80° slanted sidewalls and round corners at the bottom of the trench as shown in Figure b. The device transfer curves shown in linear and semi‐log plots are shown in Figure c and exhibit a device threshold voltage of ≈8 V and an I on / I off ratio of 10 7 approaching that of recently developed GaN‐on‐GaN trench‐gate MISFETs . The device output curves are shown in Figure d exhibiting good saturation characteristics and R on value of 31.5 mΩ cm 2 with a gate width of 100 µm (50 µm × 2; see the Supporting Information).…”
mentioning
confidence: 97%
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“…The gate recess utilized a sequential dry and wet etching in order to result in smooth and ≈80° slanted sidewalls and round corners at the bottom of the trench as shown in Figure b. The device transfer curves shown in linear and semi‐log plots are shown in Figure c and exhibit a device threshold voltage of ≈8 V and an I on / I off ratio of 10 7 approaching that of recently developed GaN‐on‐GaN trench‐gate MISFETs . The device output curves are shown in Figure d exhibiting good saturation characteristics and R on value of 31.5 mΩ cm 2 with a gate width of 100 µm (50 µm × 2; see the Supporting Information).…”
mentioning
confidence: 97%
“…The device output curves are shown in Figure d exhibiting good saturation characteristics and R on value of 31.5 mΩ cm 2 with a gate width of 100 µm (50 µm × 2; see the Supporting Information). The modest hysteresis observed in the transfer curves (Figure S13, Supporting Information) and the relatively high R on observed for these first vertical GaN‐on‐Si trench MOSFETs can be further optimized with gate surface treatments and regrowth, and with engineering the doping profile in the drift layers . Additional work is also required for device edge termination in order to achieve high breakdown voltages in these devices.…”
mentioning
confidence: 99%
“…Several prominent concepts for vertical GaN transistors are considered: Current Aperture Vertical Electron Transistors (CAVETs), Regrown Semipolar channel and p ‐type gate structure, Trench‐gate MOSFET, and Vertical FinFETs . A particular challenge of the first two concepts is the epitaxial regrowth and limited blocking capability.…”
Section: Introductionmentioning
confidence: 99%
“…On the other hand, it requires a robust gate insulating layer to allow a space charge region for channel inversion and for good transport properties close to the semiconductor‐insulator interface . Improvement of both at the same time may be achieved by MOVPE regrowth of GaN channel and gate oxide in one additional step . And again, an additional epitaxial growth step is required and the threshold voltage shift is strongly dependent on the gate voltage stress .…”
Section: Introductionmentioning
confidence: 99%
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