In-situ surface preparation of InP-based semiconductors prior to direct UVCVD silicon nitride deposition for passivation purposes

Influences of Gate Recess Structure on the DC Characteristics of 0.1 Micron Metamorphic HEMTs

“…3 (a). The corresponding calculation for N i yielded ~3×10 12 /cm 2 in our case, which is pretty close to the values observed in many other material systems (6)(7)(8)(9)(10). Therefore, it is reasonable to assume that the reduction in I dss is attributable to the negative interface charges due to deep-level states with a ~3 × 10 12 /cm 2 area density.…”

“…This is because the interface trap formation is unavoidable in the case of wide-gate recess structure, as shown in Fig 4 . In many other material systems, such as Si/SiO 2 , SiC/SiO 2 , Si/SiO 2 , InP/SiN x , and GaInSb/native oxide, the presences of acceptor-type deep-level interface traps have been already reported with a typical area density of ~1 × 10 12 /cm 2 (6-10). The origin of these interface traps can be associated with various physical causes, such as mechanical stress in the films, undesired native oxides between the semiconductors and the films, and creation of the structural defects during the film deposition (9,11,12). When these interface traps produce deep-level states, we can assume that electrons occupy most of these acceptor-type traps and behave as negatively fixed charges under device operation.…”

Electrical properties of metal–insulator–semiconductor structures with silicon nitride dielectrics deposited by low temperature plasma enhanced chemical vapor deposition distributed electron cyclotron resonance

“…It is relatively low owing to the simple chemical cleaning performed on InP surface before deposition. To reduce the interface state density, various surface passivation techniques have been used, 36,[39][40][41][42][43] including sulfur treatment. A comparison of D it obtained with different treatments and deposition processes is shown in Table IV. As explained by Landheer, 42 the very low values of D it (Ͻ10 11 eV Ϫ1 cm Ϫ2 ) calculated with the Terman method should be treated with caution.…”

Passivation of InP-based HBTs for high bit rate circuit applications

“…Table 1 gives the quality factor G, obtained for large area devices. All silicon nitrides deposited by either PECVD or UVCVD lead to a very low value of G. Various surface treatments (NH3, XeF2) prior to SiN, deposition by UVCVD (which gave good results for HFET's and photodiodes [ 6 ] ) , were tested, but did not lead to any improvement for the HBT. ' …”