2011
DOI: 10.1002/pssc.201100241
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InAs/AlGaSb heterojunction tunnel field‐effect transistor with tunnelling in‐line with the gate field

Abstract: The first fabrication of a III‐V tunnel field‐effect transistor (TFET) with tunneling directed perpendicular to the gate is reported. This new transistor geometry utilizes an InAs/Al0.45Ga0.55Sb staggered‐gap tunnel junction intended for high on current and steep subthreshold swing. The first measurements of the transistor transport properties at room temperature and ‐50 °C are provided. Tunneling transport is confirmed by the observation of negative differential resistance in the tunnel junction in the forwar… Show more

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Cited by 43 publications
(22 citation statements)
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“…Spatially separated confinement of electrons and holes, signature of type-II band alignment, initiated InAs/GaSb core-shell nanowires realization [174,175]. Field-effect transistors (FETs) [176,177] and thermo photovoltaic (TPV) [178] T2SL devices are another examples of unconventional applications of T2SL material system.…”
Section: Discussionmentioning
confidence: 99%
“…Spatially separated confinement of electrons and holes, signature of type-II band alignment, initiated InAs/GaSb core-shell nanowires realization [174,175]. Field-effect transistors (FETs) [176,177] and thermo photovoltaic (TPV) [178] T2SL devices are another examples of unconventional applications of T2SL material system.…”
Section: Discussionmentioning
confidence: 99%
“…Al 0.45 Ga 0.55 Sb source with W AlGaSb = 10 nm and InAs channel and drain with T InAs = 4 nm. This aluminum composition is chosen to match both with experiments [1] and with previous simulations [4]. The W AlGaSb and T InAs are fixed for all the simulations unless otherwise stated.…”
Section: Methodsmentioning
confidence: 99%
“…Experimental demonstrations of TFETs with p-type AlGaSb and n-type InAs [1], [2] with gate field in-line with the tunneling direction (in-line TFET) have been performed, and these devices have also been simulated based on the drift-diffusion and the dynamic nonlocal (DNL) path band-to-band model [3]. These DNL simulations have projected that the optimized device designs with an undercut length of 10 nm could achieve a minimum SS of 7 mV/decade [4].…”
Section: Introductionmentioning
confidence: 99%
“…The double peak re- sults from the subbands of the quantized InAs layer, which is sandwiched between the ZrO 2 gate oxide layer and the wideband gap AlSb layer [21]. Performance comparison of published III-V TFETs is shown in Table I (see Refs. [6], [8]- [11], [17], [19], [25], [26]). …”
Section: Electrical Characterization Of Overlap Gate Devicementioning
confidence: 99%