InAs–Si Nanowire Heterojunction Tunnel FETs

Moselund, Kirsten E.; Schmid, Heinz; Bessire, Cedric; Björk, Mikael; Ghoneim, H.; Riel, Heike

doi:10.1109/led.2012.2206789

Cited by 130 publications

(59 citation statements)

References 15 publications

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“…[5][6][7][8] III-V nanowire/Si heterojunctions with less dislocations have been achieved due to recent progress in epitaxial techniques such as selective-area growth (SAG) regardless of any mismatch in lattice constant and thermal coefficients, which have enabled the integration of III-V NWs on Si with precise positioning and vertical alignment. [9][10][11] This nm-scaled heteroepitaxy has produced inherently abrupt junctions across the III-V nanowire and Si and has demonstrated the potential of steep subthreshold slope (SS) switches using InAs NW/Si heterojunctions.…”

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confidence: 99%

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Current increment of tunnel field-effect transistor using InGaAs nanowire/Si heterojunction by scaling of channel length

Tomioka

Fukui

2014

Applied Physics Letters

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confidence: 99%

“…5,6,8,12 Thus, we have to discuss the feasibility of using other III-V NW/Si heterojunctions for future TFET applications. In this regard, InGaAs NW/Si heterojunctions are good candidates to utilize for TFET applications because InGaAs has bandgap tuning capabilities, allowing narrow InAs-and wide GaAs-like band structures.…”

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confidence: 99%

Current increment of tunnel field-effect transistor using InGaAs nanowire/Si heterojunction by scaling of channel length

Tomioka

Fukui

2014

Applied Physics Letters

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“…Second, nanowire devices can be constructed both in a horizontal and vertical arrangement. Both features have been exploited in [86,87] where CMOS compatible nanowire structures using a Si/InAs heterostructure as a building block for TFETs are demonstrated.…”

Section: Electron Devices Based On Silicon Nanowiresmentioning

confidence: 99%

Silicon Nanowires: Fabrication and Applications

Mikolajick

Weber

2015

NanoScience and Technology

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Due to the high surface to volume silicon ratio and unique quasi onedimensional electronic structure, silicon nanowire based devices have properties that can outperform their traditional counterparts in many ways. To fabricate silicon nanowires, in principle there are a variety of different approaches. These can be classified into top-down and bottom-up methods. The choice of fabrication method is strongly linked to the target application. From an application point of view, electron devices based on silicon nanowires are a natural extension of the downscaling of a silicon metal insulator semiconductor transistor. However, the unique properties also allow implementing new device concepts like the junctionless transistor and new functionalities like reconfigurability on the device level. Sensor devices may benefit from the high surface to volume ratio leading to a very high sensitivity of the device. Also, solar cells and anodes in Li-ion batteries can be improved by exploiting the quasi one-dimensionality. This chapter will give a review on the state-of-the-art of silicon nanowire fabrication and their application in different types of devices.

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“…However, the ON-OFF ratio falls short of requirements for various ITRS technologies (http://www.itrs.net/Links/2012ITRS/Home2012.htm). The main reason for the poor off-state current is the leakage current through the Schottky barrier (Franklin et al, 2012a,b) and III-V devices (Gu et al, 2012;Dey et al, 2013) (Zhou et al, 2012;Dey et al, 2013;Moselund et al, 2012;Hu, 2008;Wang et al, 2010;Ganapathi and Salahuddin, 2011;Gnani et al, 2011;Tomioka et al, 2012). The ITRS targeted values for low operating power (LOP) and high performance (HP) technologies are highlighted (http://www.itrs.net/Links/2012ITRS/Home2012.htm).…”

Section: Itrs Requirements-2024mentioning

confidence: 99%