Incorporating Bottom-Up Approach Into Device/Circuit Co-Design for SRAM-Based Cache Memory Applications

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Nanosheet field effect transistor (NSFET) has emerged as a promising candidate to replace FinFET devices at sub-7 nm technology nodes and for different SoC applications. In this work, we have investigated the DC properties of 3D vertically-stacked NSFET including the impact of self-heating effect (SHE) and also the influence of geometry scaling. The thermal resistance and the maximum lattice temperature have been analyzed according to the device’s channel number. Also, the distribution of lattice temperature has been exposed. During the 3D investigation, it has been observed that SHE degrades the switching performance and subthreshold swing SS≈22%. Furthermore, it is found that the proposed device is showing improved figure of merits as ION (~2.77×10-5A), IOFF (~10-20A), SS (>60mV/decade) and ION/IOFF (~1015). The DIBL has been reduced by -52% when the NS’s width ranges from 10 to 5 nm, and increased from 32 to 92 mV/V when the gate-length decreases from 14 to 8 nm.

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confidence: 99%

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confidence: 99%

Impact of the Self-Heating Effect on Nanosheet Field Effect Transistor Performance

Smaani¹,

Paras²,

Rahi³

et al. 2023

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“…20 Moreover, NSFET with thinner gate oxides can improve performance significantly. [21][22][23] Additionally, NSFETs can change the drain currents by modifying the NS width, providing a layout design that is compatible with CMOS. While preserving a low-cost area, the width of the NS can be tailored to match the necessary current drivability for any device across a single wafer.…”

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confidence: 99%

Gate Stack Analysis of Nanosheet FET for Analog and Digital Circuit Applications

Kumari,

Vijayvargiya,

Upadhyay

et al. 2023

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This manuscript demonstrates the performance comparison of vertically stacked nanosheet FET with various high-k materials in gate stack (GS) configuration. As the high-k dielectric materials are inevitable to continual scaling, in this paper, various high-k dielectric materials such as Si3N4, Al2O3 and HfO2 are incorporated in the GS, and the performance is studied. Further, DC and Analog/RF performance metrics are discussed in detail, and it is noticed that by using HfO2 in high-k GS, the on current (I ON) is enhanced by 46.7% and off current (I OFF) is decreased by 81.6% as compared to conventional NSFET (C-NSFET) without high-k GS. Also, the switching ratio (I ON/I OFF) is increased by 8× from SiO2 to HfO2, ensuring good logic applications. Moreover, compared to the C-NSFET, GS-NSFET with HfO2 offers better values for analog metrics like transconductance (gm) and transconductance generation factor (TGF). However, as the k value increases, the capacitances are also observed to be increased. As a result, the intrinsic delay (τ) increases by 9%, 6% and 20% from SiO2 to Si3N4, Si3N4 to Al2O3, Al2O3 to HfO2, respectively. On top of that, the circuit level demonstration is also performed for resistive load based inverter and ring oscillator (RO) for both C-NSFET GS NSFET with HfO2 as GS material. From circuit analysis, it is observed that by using the GS, the performance of the inverter is increased in terms of noise margins and DC gain. However, the oscillation frequency (f OSC) of 3-stage RO is decreased by 14.7% with the incorporation of GS owing to the increment in gate capacitance (Cgg). Consequently, the results will give deep insights into the performance analysis of NSFET with various high-k materials in gate stack at both device and circuit levels.

“…[1][2][3][4][5][6][7][8][9][10] After observation and experimental verification of negative capacitances (NC) in ferroelectric materials (Fe), subthreshold swing based research and development has been taken seriously by semiconductor research community. [10][11][12][13][14][15] The ferroelectric materials based research&development, [11][12][13][14][15][16] provides a big domainto overcome the classical limitations [17][18][19][20][21][22] of conventional CMOS technology for low power. The non-identical polarization entire-near conventional dielectric, help to boost up the electricbeyond the end of the silicon roadmap.…”

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confidence: 99%

“…This indicates optimization is needed for desirable design. Genetic algorithm found suitable used for optimization.In thisresearchwork, we have used genetic algorithm (GA) for optimization of desirable device design parameters like I ON , SS, I amb [17][18][19][20][21][22][23][24][25][26][27][28] for ferroelectric tunnel FET.…”

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confidence: 99%

Optimization for Device Figure of Merit of Ferroelectric Tunnel FET using Genetic Algorithm

Guenifi

Rahi

Benmahdi

et al. 2023

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A tunnel field effect transistor (TFET) is a gate-controlled, band to band tunneling (BTBT) transport of charge carriers having low subthreshold swing(SS < 60 mV/decade|T = 300K). With TFETs, low-ION is a built-in problem which limits its adaptability to high-speed, low-power uses. To overcome this limitation, a conventional double-gate TFET was constructed having ferroelectric (BaTiO3)/HfO2 gate materials and a source/channel region with Si1-xGex/Si semiconductor channel composition. This design enhances the ION and lowers the subthreshold swing (SS). Analysis using the Silvaco simulator shows improvement in ION current approximately 103 times better than that of conventional DGTFET, without affecting IOFF. Ultimately, a change in ION from 10-8 A/µm to 10-5 A/µ was measured for VDS~0.5 V at room temperature. IOFF of ~10-20 A/µm was measured. In addition to this, a first time genetic algorithm has been used for the optimization of ferroelectric TFET (Fe-TFET) device design parameters like a subthreshold swing (SS), ambipolar current (Iamb), and ION by using device design parameters, doping (NS, ND), dielectric (εOX), and work function (WF). This research shows that Fe-Tunnel can play a leading role for super-low-power applications in advanced VLSI circuits and systems.