Increasing Microprocessor Speed by Massive Application of On-Die High-K MIM Decoupling Capacitors

Sanchez, H.; Johnstone, Brittany; Roberts, D.; Mandhana, O.P.; Melnick, B. M.; Celik, M.; Baker, Michael; Hayden, J.D.; Min, Byung-Jun; Edgerton, Jeremy R.; White, B.

doi:10.1109/isscc.2006.1696280

Cited by 15 publications

(8 citation statements)

References 2 publications

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“…This problem is further exacerbated in SOI for small, fast die due to the inherent junction capacitance and well-capacitance loss relative to the bulk silicon. Sanchez et al [9] have reported results of the implementation of a massively pervasive on-die metal high-k insulator-metal decoupling capacitor (high-k MIM capacitor) for improved processor core maximum frequency.…”

Section: Mim Capacitormentioning

confidence: 99%

TSV Decoupling Schemes

Song

Pak

Kim

2014

Electrical Design of Through Silicon Via

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Three-dimensional (3D) through silicon via (TSV) technologies promise increased system integration at lower cost and reduced footprint, as well as increased system bandwidth. Three-dimensional TSV may be implemented by simply adapting current silicon fabrication and package technologies. There is a strong demand for 3D, high-density and the heterogeneous integration of silicon and passive components because 3D integrated circuit (3D ICs) increase layout complexity due to the needs for additional solution space, as well as increased power density and power noise issues. To overcome the I/O speed limitation related to the above power problems in 3D ICs, on-chip decoupling capacitors and passive components used in the packaging have been implemented using TSV technologies. In this chapter, TSV decoupling schemes are introduced, showing that they have prominent advantages relative to reducing the inductive power distribution network (PDN) impedance and suppressing power noise such as the simultaneously switching noise (SSN) in the 3D ICs.

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Section: Mim Capacitormentioning

confidence: 99%

TSV Decoupling Schemes

Song

Pak

Kim

2014

Electrical Design of Through Silicon Via

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“…Unlike CMOS capacitors that are built in the device layer, MIM capacitors are fabricated between metal layers. These structures have high capacitance density and low leakage current density [3,18,34,35,40,50]. However, MIM decaps cannot be used unconditionally to replace CMOS decaps, since their use incurs a cost: they present routing blockages to nets that attempt to cross them.…”

Section: Decap Allocationmentioning

confidence: 99%

Thermal and Power Delivery Challenges in 3D ICs

Jain

Zhou

Kim

et al. 2009

Integrated Circuits and Systems

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Compared to their 2D counterparts, 3D integrated circuits provide the potential for tremendously increased levels of integration per unit footprint. While this property is attractive for many applications, it also creates more stringent design bottlenecks in the areas of thermal management and power delivery. First, due to increased integration, the amount of heat per unit footprint increases, resulting in the potential for higher on-chip temperatures. The task of thermal management must necessarily be shared both by the heat sink, which transfers internally generated heat to the ambient, and by using thermally conscious design methods. Second, the power to be delivered to a 3D chip, per package pin, is tremendously increased, leading to significant complications in the task of reliable power delivery. This chapter presents an overview of both of these problems and outlines solution schemes to overcome the corresponding bottlenecks.

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“…Unlike CMOS capacitors that are built in the device layer, MIM capacitors are fabricated between metal layers. These structures have high capacitance density and low leakage current density [20]- [25]. However, MIM decaps cannot be used unconditionally to replace CMOS decaps, since their use incurs a cost: they present routing blockages to nets that attempt to cross them.…”

Section: Introductionmentioning

confidence: 99%

“…MIM Decaps MIM decaps are typically useful for MPUs, RF capacitors in high frequency circuits, as well as filter and analog capacitors in mixedsignal products [23]. Recently, several successful implementations of high-performance MIM decaps have been reported in [20]- [25]. In [23], a high reliability MIM capacitor is reported to be integrated into a 0.18μm CMOS foundry technology using copper interconnects.…”

Section: Introductionmentioning

confidence: 99%

Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors

Zhou

Sridharan

Sapatnekar

2009

2009 Asia and South Pacific Design Automation Conference

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Abstract-In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise problem, already a major issue in 2D, is even more severe in 3D. CMOS decoupling capacitors (decaps) have been used effectively for controlling power grid noise in the past, but with technology scaling, they have grown increasingly leaky. As an alternative, metal-insulator-metal (MIM) decaps, with high capacitance densities and low leakage current densities, have been proposed. In this paper, we explore the tradeoffs between using MIM decaps and traditional CMOS decaps, and propose a congestion-aware 3D power supply network optimization algorithm to optimize this tradeoff. The algorithm applies a sequence-of-linear-programs based method to find the optimum tradeoff between MIM and CMOS decaps. Experimental results show that power grid noise can be more effectively optimized after the introduction of MIM decaps, with lower leakage power and little increase in the routing congestion, as compared to a solution using CMOS decaps only.

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Increasing Microprocessor Speed by Massive Application of On-Die High-K MIM Decoupling Capacitors

Cited by 15 publications

References 2 publications

TSV Decoupling Schemes

TSV Decoupling Schemes

Thermal and Power Delivery Challenges in 3D ICs

Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors

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