Increasing the robustness of CUDA Fermi GPU-based systems

Carlo, Stefano Di; Gambardella, Giulio; Indaco, Marco; Martella, Ippazio; Prinetto, P.; Rolfo, Daniele; Trotta, Pascal

doi:10.1109/iolts.2013.6604088

Cited by 7 publications

(3 citation statements)

References 10 publications

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“…Moreover, the same method was partially applied to functionally test the special function units (SFUs) in the GPGPUs. Other works introduced application robustness [31] and mitigation strategies [32] for the data-path modules. Those methods employed combinations of high-level languages and in-line assembly code again.…”

Section: Related Work In the Areamentioning

confidence: 99%

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

2020

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The highly parallel processing capabilities and reduced power performance of General Purpose Graphics Processing Units (GPGPUs) have been crucial factors for their massive use in multiple fields, such as multimedia and high-performance computing applications. Nowadays, more demanding areas, such as automotive, employ GPGPU devices where safety and reliability are mandatory design constraints. Nevertheless, the structural complexity, the transistor density, and the implementation in the latest silicon technologies introduce challenges to match safety and reliability requirements. In these technologies, wear-out and aging are factors that may significantly increase the occurrence of permanent faults during the lifetime operation. Moreover, these faults may generate unacceptable misbehaviors during the execution of an application. These constraints require devising new methods for in-field fault detection, thus verifying the integrity and correct behavior of the device during its whole operational life. This work proposes a technique to generate functional self-test programs targeting the detection of permanent static faults in the memory of the warp scheduler of a GPGPU. The proposed technique can translate fault primitives, which represent the effect of faults in a memory cell, into self-test functions and programs composed of a sequence of operations to excite the fault in the memory and to propagate its effects to a visible location, thus detecting its presence. We focused on the memory in the warp scheduler because it represents a crucial module for the device operation. Furthermore, this memory is present in each Streaming Multiprocessor (SM) of a GPGPU. Some experimental results to validate the method have been gathered, resorting to the NVIDIA Visual Profiler and the Nsight Debugger using the NVIDIA-GEFORCE GTX GPU platform and a structural fault simulator. The CUDA programming environment was used to implement the test procedures. INDEX TERMS Functional test, general purpose graphics processing units (GPGPUs), memory test, software-based self-test (SBST).

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Section: Related Work In the Areamentioning

confidence: 99%

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

2020

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“…Program duplication was employed in the past by duplicating the execution of the entire program [11]. Similarly, the authors in [7] targeted faults affecting the general-purpose register files in the GPU by replicating the whole assembly code in an intertwined fashion and reaching up to 99% error reduction at a performance cost of up to 78%.…”

Section: A Software-based Hardening Techniques For Gpusmentioning

confidence: 99%

Analyzing the Sensitivity of GPU Pipeline Registers to Single Events Upsets

Condia¹,

Goncalves²,

Azambuja³

et al. 2020

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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Graphics processing units are available solutions for high-performance safety-critical applications, such as selfdriving cars. In this application domain, functional-safety and reliability are major concerns. Thus, the adoption of fault tolerance techniques is mandatory to detect or correct faults, since these devices must work properly, even when faults are present. GPUs are designed and implemented with cutting-edge technologies, which makes them sensitive to faults caused by radiation interference, such as single event upsets. These effects can lead the system to a failure, which is unacceptable in safetycritical applications. Therefore, effective detection and mitigation strategies must be adopted to harden the GPU operation. In this paper, we analyze transient effects in the pipeline registers of a GPU architecture. We run four applications at three GPU configurations, considering the source of the fault, its effect on the GPU, and the use of software-based hardening techniques. The evaluation was performed using a general-purpose soft-core GPU based on the NVIDIA G80 architecture. Results can guide designers in building more resilient GPU architectures.

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“…Other works introduced functional tests [17,18], fault detection [19][20][21][22], and mitigation [23][24][25] strategies only based on software mechanisms. These solutions are effective in detecting most faults and tolerating a high percentage of them.…”

Section: Introductionmentioning

confidence: 99%

A dynamic reconfiguration mechanism to increase the reliability of GPGPUs

Condia

Narducci

Reorda

et al. 2020

2020 IEEE 38th VLSI Test Symposium (VTS)

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1 -General Purpose Graphic Processing Units (GPGPUs) are effective solutions for high-demanding data processing applications. Recently, they started to be used even in safety-critical applications, such as autonomous car driving systems. GPGPUs are implemented using the latest semiconductor technologies, which are more prone to faults arising during the lifetime operation. However, until now fault mitigation solutions were not extensively included in GPGPUs, due to the limited reliability requirements of the applications they were originally intended for (e.g., gaming or multimedia). This work proposes a dynamically configurable selfrepairing mechanism aimed at mitigating the impact of permanent faults in the Scalar Processor (SP) cores in GPGPUs. The mechanism is based on spare modules that can be used to replace faulty SPs when a fault is detected. A configuration instruction allows dynamically controlling in software the selection of the set of active SPs in the SM. The method is extremely flexible since it does not require any change in the application software. Experimental results show that the solution introduces a moderate area overhead while allowing continue working even in the case of any permanent faults affecting the SPs.

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Increasing the robustness of CUDA Fermi GPU-based systems

Cited by 7 publications

References 10 publications

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

Analyzing the Sensitivity of GPU Pipeline Registers to Single Events Upsets

A dynamic reconfiguration mechanism to increase the reliability of GPGPUs

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